Transponder monitoring system

ABSTRACT

A transponder monitoring system includes a fixed location interrogation station and transponder units carried by vehicles, with the transponder units being placed in an activated transmit mode in response to interrogation pulses transmitted by the interrogation station. The messages received at the interrogation station are verified by the transmission of verification pulses on a bit by bit basis, with failure of verification causing a vehicle transponder unit to be reset to begin transmission over again. This permits an orderly response from the vehicle units to be obtained even though several units may be within the interrogation field at the same time and may be simultaneously attempting to transmit information to the interrogation station. Upon completion of transmission of an error free (verified) message from a transponder, the transponder is disabled from further transmission until the vehicle leaves the interrogation field.

United States Patent Dame [4 1 June 13, 1972 [54] TRANSPONDER MONITORINGSYSTEM Primary Examiner-Charles E. Atkinson 72 Inventor: John s. Dame,Oak Park, 111. Achele [73] Assignee: Motorola, Inc., Franklin Park, Ill.[57] ABSTRACT 22] Filed: Aug. 28, 1970 A transponder monitoring systemincludes a fixed location interrogation station and transponder unitscarried by vehicles, [21] Appl' 67875 with the transponder units beingplaced in an activated transmit mode in response to interrogation pulsestransmitted by 340/147 34 /16 the interrogation station. The messagesreceived at the inter- [51 Int. Cl. ..G 08b 29/00 rogation station areverified by the transmission of verification 1 Field 0f Search 147pulses on a bit by bit basis, with failure of verification causing 3 150a vehicle transponder unit to be reset to begin transmission over again.This permits an orderly response from the vehicle [56] Reference Citedunits to be obtained even though several units may be within UNITEDSTATES PATENTS v the interrogation field at the same time and may besimultaneously attempting to transmit information to the interrogation3,159,816 12/1964 Tiemann ..34()/ 147 station, Upon completion oftransmission of an error free ,106 3/ 1956 Ph lps i (verified) messagefrom a transponder, the transponder is dis- 2,155,554 4/1939 146-1 xabled from further transmission until the vehicle leaves the in- Pettitt1 X [en-ogation 3,513,443 5/1970 Anderson... ..340/ 163 X m- 4 MASTERSTABLE 050.

TRIGGER 67 NOR i NOR 25 Claims, 6 Drawing Figures TRANSMITTER DRIVER ENDOF BISTABLE ACT TRANSPONDER MONITORING SYSTEM BACKGROUND OF THEINVENTION It often is desirable to identify and monitor moving vehiclesfrom a fixed location in order to determine the location of the movingvehicles at periodic intervals and also to determine variableinformation relating to particular conditions to be monitored in thevehicles. In addition there is a need for monitoring a number of fixedtransponders from a central location, or from a mobile interrogationunit, such as an automatic meter reading system. Several techniques havebeen developed for accomplishing these results, for example such assending a coded message to the vehicle or fixed transponder identifyingthe vehicle or transponder and requesting a response from it. Thevehicle or transponder, upon receipt of its unique code, then provides areply to the monitor. Such a technique however, generally requires thatthe vehicle or transponder have relatively sophisticated electronicequipment; and where large numbers of vehicles or transponders areinvolved, the cost of such a system can be prohibitive. In addition thistechnique requires some advance information concerning a vehicle ortransponder, so that it may be directly and properly addressed at theproper time; and when a large number of unique address codes must betransmitted by the monitor, a severe timing restriction exists. I

Where a large number of transponders are to be interrogated atsubstantially the same time, such as in a railroad freight train inwhich the freight cars are to be monitored or in a meter monitoringsystem, normal radio communication presents problems unless a selectiveaddress coding scheme for each of the transponders is used. Since manyof the transponders may receive the interrogation signalssimultaneously, there must be some means by which the reply from onetransponder can be separated from that of another in time or frequency.All of these requirements have caused radio transmission equipment tobecome very costly for this type of monitoring.

Systems involving a lower cost for vehicle units have been proposed inwhich the use of color coding is employed for the identification andmonitoring of vehicles such as railroad freight cars, the number ofwhich is high and which may be arranged in any random order in anyparticular train. In such systems, color signal patches are positionedon each of the freight cars which are to be monitored by a highlydirective light beam positioned alongside the track. Although colorcodedpatches are relatively inexpensive and also provide means foridentifying each of the cars without interference from another, thereare several drawbacks to color coding systems. For example, thedirective light beam is reflected from other parts of the cars as theypass, so that the coding scheme used must be more complex than would berequired if only the color patches were scanned by the light beam inorder to distinguish the color coded signal from background noise.

' ln addition fading of the code patches and extreme weather conditions,such as ice and snow, require that the code patches have sufficientredundancy to permit the message to be read, even through parts of thecode patch are missed or obscured. Even if such redundancy is provided,however, the patches may become temporarily obliterated or the trackside unit may become blocked, rendering the system temporarilyinoperative.

In the interests of operating simplicity and cost, it may be desirableto accept these limitations of color-code patch systems. The code patchsystems, however, have other limitations which are unacceptable for somemonitoring requirements. For example, with refrigerator freight carswhich are to be monitored to determine whether or not the ears areoperating properly and the temperature inside is within predeterminedsafe ranges, a more complex system than can be provided by this simplecode patch is required, since simple code patch systems only providefixed infonnation such as car or vehicle identification.

The code patch method can provide variable information relating to thetemperature of refrigerator cars and the like by placing the code patchon a revolving drum, with the particular code displayed indicating theinformation concerning the car which is to be monitored. Thus, asconditions within the car change, the drum rotates to change the codesignal which is presented for interrogation by the track-side unit.Although a rotating drum system may be made to convey the desiredinformation, the cost factors which dictate the use of the code patchwhen a simple identification interrogation is the only requirement makethe use of the drum containing the code patch very much less attractive.This results from the increased cost of the mechanical apparatus whichis required to position the drum. In addition, since the order anddirection in which the cars are placed in a freight train is random andsince the railroad cars or the piggy-back truck trailers can bepositioned in either direction on the train, either two code patch drumsare required, one on each side of the car, or interrogat' ing orscanning units must be placed on both sides of the track at eachinterrogation location. Even if a code patch drum system is employed,the problems of the sensitivity of this system to the position of thecode patch and to weather are not overcome. Further the reliability ofoperation of the necessary mechanical apparatus in extreme weatherconditions and under the extreme vibration to be found in theenvironment of the freight car is questionable.

As a consequence, it is desirable to provide a radio transmission systemrequiring minimal sophistication in the transponder located in thefreight car or piggyback trailer, so that the advantages of radiotransmission may be realized without the attendant prohibitive cost forthe transponder units ordinarily associated with such systems. Inaddition it is desirable to minimize the requirement of the vehicleidentification coding to be transmitted by the interrogation station tothe vehicle for initiating a response from the vehicle transponder, sothat the station decoding equipment can be substantially simplified.

SUMMARY OF THE INVENTION Accordingly it is an object of this inventionto provide an improved transponder identification and monitoring system.

It is another object of this invention to provide a transponderidentification and monitoring system with verification at thetransponder of the accuracy of the received message at an interrogationstation.

It is an additional object of this invention to use a uniqueverification code sequence for error checking messages transmitted froma transponder to an interrogation station on a bit!- by-bit basis.

It is yet another object of this invention to employ a buffer storagecircuit in an interrogation station permitting the storage and removalof messages therefrom at different bit rates to accomodate differencesin the rate of transmission from a transponder and the rate at whichdata can be utilized by a utilization device.

In accordance with a preferred embodiment of this inven tion, asignalling system identifies and monitors a transponder unit whichoperates to transmit a unique message in response to receipt of atransmitted interrogation signal. An interrogation unit continuouslytransmits an interrogation signal until a transponder unit responds, anda receiver at the interrogation unit receives the message from atransponder.

The interrogation unit includes a circuit responsive to the reception ofthe message from a transponder and transmits a verification signalcorresponding to the signal train received by the interrogation unitreceiver circuit. In the transponder unit, the verification signal iscompared with the message signal train supplied from the transponder;and the comparison circuit produces an output upon failure of averification. In the transponder this output causes the transponder unitto reset and cease transmission of the message. At the interrogationstation, the resetting of a transponder (resulting in imrum m-n thefailure of data to be received as expected) causes reversion of theinterrogation station to an interrogation mode of operation.

In a more specific embodiment, the interrogation station furtherincludes a buffer storage circuit for temporarily storing receivedmessages, with the storage of the messages in the buffer storage circuitbeing at one bit rate with the removal of messages from the bufferstorage circuit for utilization being effected at a different bit rate.

BRIEF DESCRIPTION OF THE DRAWING FIG. I is a block diagram of aninterrogation station;

FIG. 2 is a block diagram of a transponder unit for operation inconjunction with the interrogation station shown in FIG. 1;

FIG. 3 illustrates the different signals transmitted by theinterrogation station shown in FIG. 1 and the transponder unit shown inFIG. 2.

FIG. 4 shows typical message sequences for different modes of operationof the circuits shown in FIGS. 1 and 2;

FIG. 5 is a detailed block diagram of the system logic portion of thecircuit shown in FIG. I; and

FIG. 6 is a block diagram illustrating a buffer storage circuit for usein conjunction with the circuits shown in FIGS. 1 and 5.

DETAILED DESCRIPTION Referring now to the drawings, there is shown inFIG. I a functional block diagram of an interrogation station tracksideunit of a type which may be provided at fixed locations to be passed byvehicles to be interrogated. In conjunction with a railway system, theinterrogation station could be located along the right-of-way of thetrains including cars which are to be monitored. Each of the vehicles tobe monitored by the interrogation station shown in FIG. I carries atransponder of the type illustrated in FIG. 2.

In the trackside interrogation station, a master frequency oscillator I0is utilized to provide all of the operating frequencies for the system,including the vehicle transponder illustrated in FIG. 2.

The master frequency oscillator 10 is controlled by data input signalsfrom a data input and system logic circuit 11 which supplies a sequenceof two level signals to the master frequency oscillator I0. Thesesignals cause the frequency of the oscillator I0 to shift between twofrequencies, so that its output is an FSK output signal. This output issupplied through two divide by-three circuits 14 and 15 to a poweramplifier circuit 16, which supplies the output signals from theinterrogation station over a transmitting antenna 17. For the purposesof illustration, the transmitter frequencies supplied from the antenna17 may be considered 47.25 kilohertz for mark" information, and 45.75kilohertz for space" information, the terms mark" and space" being usedmerely to distinguish the two different states of the output signals.

The output of the frequency divider 15 also is supplied through anotherdivide-by-three frequency divider 19 and a divide-by-l6 frequencydivider 21 to provide data clock signals to the data input and systemlogic for operating that logic. Thus, the data input and system logicfrequency is controlled directly by the master frequency oscillator 10.

In addition to supplying the FSK signals which are transmitted from theinterrogation station, the output of the master frequency oscillator 10is also supplied through a divide-bytwo frequency divider 24 whichsupplies the injection frequencies to a mixer 25 located in theinterrogation station receiver circuit 26. Signals received by thereceiver circuit 26 are applied from a receiver antenna 27 to a bandpass amplifier 28. The output of the mixer 25 then is supplied throughfrequency selective amplifying circuit 30 to a first peak detector 31,with the output of the amplifier 30 also being supplied to a furtheramplifier 32 which provides input signals to a second peak detector 33.

The input signals which are supplied to the antenna 27 and whichultimately determine the magnitude of the signals stored in the peakdetectors 31 and 33 are supplied to the antenna 27 from the transpondershown in FIG. 2. The interrogation station shown in FIG. 1 maycontinuously transmit interrogation code sequences in the form of twolevel FSK signals in accordance with a predetermined pattern generatedby the data input and system logic I l. The particular format of thispattern may vary to suit the particular operating requirements of thesystem employing the interrogation station and transponder shown inFIGS. 1 and 2, but preferably is in the format shown in waveform A ofFIG. 3.

The signals transmitted from the antenna 17 of the interrogation stationare received in the transponder on an antenna 50 (FIG. 2) when thevehicle carrying the transponder comes close enough to the interrogationstation to receive such signals. These signals are supplied through anRF amplifier state 51 to a low pass filter 52 which has a passcharacteristic chosen to prevent signals transmitted by the transpondercircuit and received by the antenna 50 from being passed thereby. Theoutput of the filter 52 is applied through an additional amplifier stage54 to the set" input of a bistable multivibrator 56, so that a set"pulse is applied to the input of the multivibrator 56 for each cycle ofthe received FSK input signals.

Included in the transponder is a variable frequency transponderoscillator 60, the frequency of which is controlled by a DC controlvoltage applied over a lead 61 to the oscillator 60, with the outputfrequency of the oscillator 60 selected to be four times the frequencytransmitted by the interrogation station. The output of the transponderoscillator 60 is applied to a transmitter driver circuit 63 to providethe source of operating frequency for the transmitter of thetransponder. This output also is applied through a divide-by-fourfrequency divider 64 which supplied output signals or pulses to thereset input of the bistable multivibrator 56, thereby resetting themultivibrator 56 each time that a reset pulse is applied theretofollowing the application of a set pulse to the set" input from theoutput of the amplifier 54. It should be noted that the ratio of thefrequency of the oscillator 60 to the interrogation station frequencymay be other than that selected for purposes of illustration.

In order to derive the oscillator control voltage for the transponderoscillator 60 to phase lock the frequency of operation of thetransponder oscillator 60 to the frequency of the received signalobtained from the antenna 50, the output of the multivibrator 56 isapplied through a low pass filter 57 to produce a varying DC controllevel, the magnitude of which is dependent upon relative phase shift ofthe input signals applied to the set and reset inputs from the amplifier54 and the frequency divider 64, respectively.

The output of the low pass filter 57 rapidly changes to a different DClevel when the input frequency received on the antenna 50 changes inaccordance with the FSK signal being transmitted from the interrogationstation antenna 17. This change is DC level is applied over theoscillator control lead 61 to the oscillator 60 to shift the frequencyof the transponder oscillator 60 until the frequency of the oscillator60 is four times the received input frequency. When this condition isreached, the DC output of the low pass filter 57 stabilizes at theparticular level established by the transmitted frequency from theinterrogation station.

This changing DC level from the low pass filter 57 also is appliedthrough an amplifier 67 to a Schmitt trigger circuit 68, the output ofwhich is a reconstructed two level signal, corresponding to the mark andspace" input signals applied to the master frequency oscillator 10 fromthe data input and system logic II in the interrogation station. Thisreconstructed signal train from the output of the Schmitt triggercircuit 68 is utilized in the transponder circuit to operate thetransponder logic system.

Since the transponder unit carried by the vehicle is only required toprovide an output when it is within the range of an interrogationstation (this range being on the order of only a few hundred feet), itis not necessary that the system logic of the transponder unit beenergized continuously. In fact it is desirable that this logic normallyis not energized in order to conserve power in the vehicle. As aconsequence, the power supplied to the logic portion of the transponderunit normally is off; but when the vehicle carrying the transponderenters into the range of an interrogation station, the output of theSchmitt trigger circuit 68 changes between mark and space signal levelsin accordance with the signals being received on the antenna 50 by thetransponder. This activity is applied from the Schmitt trigger circuit68 over a lead 69 to a conventional activity check circuit 70 whichprovides an output pulse a predetennined time interval after signalactivity appears on the lead 69.

This output pulse is passed through a normally enabled inhibit gate 71to be utilized to effect the turning on of operating power for thesystem logic shown in FIG. 2. The power supply circuit and the switchenergized by the output of the inhibit gate 71 have not been shown inFIG. 2 since these circuit elements are conventional and may be embodiedin number of different forms. The activity check circuit 70 preventsaccidental turning on of logic operating power due to spurious noiseconditions and the like.

Once power has been applied to the logic portion of the circuit shown inFIG. 2, it then responds to the signals obtained from the output of theSchmitt trigger circuit 68. As stated previously, the tracksideinterrogation station normally transmits'a continuous sequence ofinterrogation pulses. As shown in waveform A of FIG. 3, these pulses arein the form of a l millisecond mark pulse followed by a 3 millisecondspace pulse, this pattern being continuously repeated. For the purposesof illustration, the mark pulse may be considered to be transmitted at a47.25 kilohertz rate, with the space pulse being transmitted at a 45.75kilohertz rate.

At the output of the Schmitt trigger circuit 68, the decoded mark andspace pulses are in the form of a high" output for mark and a low outputfor space and are applied through a pair of inverters 72 and 73 to theclamping input of an astable multivibrator 74, which provides the basictiming reference to decode signals received from the interrogationstation. When the output of the Schmitt trigger circuit 68 is a spaceoutput, the astable multivibrator 74 is clamped to an off condition ofoperation with the output then being held high." Reception of the firstmark pulse releases the multivibrator 74 for operation to produce anegative going or high to low" pulse transition 0.5 millisecondsfollowing removal of the clamp at its input. The waveform of themultivibrator 74 then becomes positive 1 millisecond after release andnegative 1.5 milliseconds after release, etc., as indicated in thewaveform shown at the output thereof.

The output signals of the multivibrator 74, are used to drive atwo-stage clock counter including a pair of bistable multivibrators 77and 78, interconnected as a conventional two stage binary counter. Thesemultivibrators 77 and 78 previously have been reset to a clear state ofoperation by the first positive-going or low-to-high space to marktransition appearing at the output of the Schmitt trigger circuit 68 andapplied thereto through the inverter 72 and a second inverter 79 causingthe Q outputs of both of the multivibrators 77 and 78 to be low at thestart of operation of the circuit and the O outputs both to be high. Thetrigger inputs to the multivibrators 77 and 78 respond to negative-goingpulse transistions; so that the pulse transition at the output of theastable multivibrator 74, occuring 0.5 milliseconds after release of themultivibrator for operation, causes the bistable multivibrator 77 tochange states with its 6 output going low and its Q output going high.This change of state of the multivibrator 77, of course, does not affectthe multivibrator 78 at this time.

When power initially is applied to the logic circuit of the transponder,a seven stage shift register circuit 80, each stage of which is a J-Kflip-flop, assumes a random count determined by the particularparameters of the different bistable stages of the register. lt isunimportant to the operation of this system what this count may be, butit will be appreciated that different transponders in different ones ofthe cars on a train will have the shift registers therein storingrandomly different counts upon the application of operating power. Thisinitial count in the register 80 then determines the address to whichthe particular transponder with which the register 80 is associated willrespond to supply data from the transponder to the interrogationstation. This is accomplished by providing the binary 1" outputs of allof the seven stages of the shift register 80 to a pair of NOR gates 81and 82, which together constitute a 7 input NOR gate.

The outputs of the NOR gates 81 and 82 are coupled together to fonn aninitiate transmission output to a transmit bistable multivibrator 83 inthe form of a pair of cross-coupled NOR gates 84 and 85, with the NORgate 84 providing a high output initially and the NOR gate 85 providinga low initial output. This state of the bistable multivibrator 83 isinsured upon the initial application of operating power to the system bycoupling one of the inputs of the NOR gate 85 to the operating potentialthrough a capacitor 86, with the junction of the NOR gate input 85 andthe capacitor 86 being coupled through a resistor to ground. Thus, whenoperating potential is initially applied to the logic circuit, apositive pulse is applied to the NOR gate 85, driving its output low.This output combines with the low output obtained from the NOR gates 81and 82 at the input of the NOR gate 84 to drive the output of the NORgate 84 high to establish the initial state of operation of the transmitbistable multivibrator 83.

Three timing NOR gates 87, 88 and 89 are provided for controlling theoperation of the transponder circuit, and the initial high output of theNOR gate 84 is applied to the NOR gates 88 and 89 to disable thesegates, causing the outputs to be held low. At the same time, the outputof the NOR gate 85 is low and is applied to the input of the NOR gate87, enabling the NOR gate 87 to operate to monitor the receivedinterrogation signals. The output of the gate 87 initially is low,however, since one of the inputs to the gate 87 is the 6 output of themultivibrator 77. A third input to the NOR gate 87 is obtained from theQ output of the multivibrator 78, which at this time also is a low orenabling input.

When the multivibrator 77 changes s t ate 0.5 milliseconds after receiptof a mark input signal, the Q output thereof goes low, causing a highoutput to be obtained from the .NOR gate 87. This in turn applied to aNOT gate 90 of a code monitor circuit 91, including a second NOR gate92, causes the NOR gate 90 to produce a low output, thereby enabling theNOR gate 92, the other input to which is obtained from the nowhighoutput of the inverter 73. At 0.5 milliseconds, the high Q output fromthe multivibrator 77 is applied through a differentiating circuit 97 tothe NOR gate 96 to cause the output of a NOR gate 96 to be driven lowand that of a NOR gate forming a multivibrator therewith to be drivenhigh.

Upon termination of the mark portion of the interrogation pulse at 1.0milliseconds, when the output of the inverter 73 goes low, a high outputis obtained from the NOR gate 92. This output is applied to one input ofthe NOR gate 95, to cause the output of the NOR gate 95 to drop from ahigh to a low value. The high-to-low transition at the output of the NORgate 95 is applied through an amplifier 98 which produces a high-to-lowtrigger pulse at its output, with this trigger pulse being applied as ashift pulse to the seven stages of the shift register 80 to shift theinformation stored in the register one stage to the right, as viewed inFIG. 2.

The otEput of the final stage of the shift register 80 is such that theQ output is low for a binary 1 stored in that stage and the Q output islow for a binary 0" stored in the final stage. These outputs areconnected, respectively to the inputs of a pair of NOR gates 100 and 101enabled by the output of the NOR gate 85 through an OR gate formed fromtwo NOR gates 163 and 164, to cause the output of the NOR gate 101 to behigh when the final or output stage of the shift register 80 is storinga binary "0" and to cause the output of the NOR gate 100 to become highwhenever the final stage of the shift register 80 is storing a binaryl." The output of the NOR gate 101 is coupled to the C input of theinput stage of the shift register 80 and the output of the NOR gate 100is inverted by a NOR gate inverter 102 and is coupled to the S input ofthe input stage. These connections cause the shift register 80 tooperate as a maximum sequence counter, with the input stage changingstate upon application of a shift pulse to the register when thepotentials applied to the S and C inputs both are low (binary l storedin the final stage) and with the input stage not changing state when theS and C inputs both are high (binary stored in the output stage).

The shift pulses which are obtained from the output of the amplifier 98also are applied to the input of a four stage binary counter 105 todrive the counter 105. At this point in the operation of the circuit,however, the counter 105 is not stepped since the low output of the NORgate 85 in the transmit bistable multivibrator 83 is applied throughthree NOR gate inverter stages 107, 108 and 109 to cause a highpotential to be applied to the reset or clear inputs of all of thestages of the counter 105, holding the counter 105 in its cleared or 0"state of operation.

Upon termination of the mark portion of the first interrogation pulse inthe sequence of interrogation pulses, the potential at the output of theinverter 73 once again becomes low, clamping the output of the astablemultivibrator 74 to a high output and terminating operation of thecounter stages 77 and 78. At the same time, the NOR gate 92 is enabledand causes a high output to appear. This output is applied to the NORgate 95 in the bistable multivibrator to cause the output thereof to golow and the output of the NOR gate 96 in the bistable multivibrator togo high with the output transition from the NOR gate 95 forming the nextshift pulse. When the next mark appears in the decoded output of theSchmitt trigger circuit 68, the multivibrators is 77 and 78 are cleared,as described previously; and the sequence of operation repeats, untilthe counter/shift register 80 stores all binary l s. In this state ofthe register 80 all of the inputs to the NOR gates 81 and 82 are low,causing a high input to be applied to the NOR gate 84 in the transmitbistable multivibrator 83. The count required to reach this state ofoperation depends' on the initial count stored in the register and maybe from one to 127. Whenever the count is reached however, a change ofstate of the bistable multivibrator 83 is forced, with the output of theNOR gate 84 going low and the output of the NOR gate 85 going high.

With the output of the NOR gate 84 being low, the code verificationgates 88 and 89 are enabled as is a transmitter key NOR gate 111. At thesame time, the interrogation NOR gate 87 is disabled by the high outputapplied thereto from the output of the NOR gate 85, causing the outputof the NOR gate 87 to be held low as an enabling input to the NOR gate90.

Upon termination of the mark portion of the interrogation pulse, a NORgate 125 is supplied with the l output of the output stage of the shiftregister 80, which now is low, and supplied with the output of theinverter 73 which is low for the space pulse portion of theinterrogation pulse as shown in waveform A of FIG. 3. Thus, the gate 125provides a high output and this output coupled to the input of a NORgate 126 produces a low output from the NOR gate 126, which is invertedby the now enabled NOR gate 111 to produce a high transmitter key pulseto the transmitter driver 63. This opens the driver 63 to provide aburst of output signals on the output antenna 65 at a frequency of 183KHZ; and this signal burst transmitted during the interrogation stationspace" pulse, corresponds to a transmitted binary l from the transponderunit and persists so long as both of the inputs of the NOR gate 125 arelow. This transmitted binary l from the transponder is shown in waveformE of FIG. 3, with the dotted line portion of waveform E indicating thatthis first binary l transmitted by the transponder is 3 milliseconds induration corresponding to the space interval of the interrogation pulseshown in waveform A of FIG. 3. Thus, it may be seen that the firstbinary data bit transmitted by the transponder always is a binary At theend of the 3 millisecond space portion of the interrogation pulse, theinterrogation station once again commences transmitting a mark pulsewhich causes the NOR gate 125 to be disabled, producing a low outputfrom the NOR gate 111 and terminating the keying of the transmitterdriver 65 to end the first mark pulse transmitted from the transponder.This next mark pulse, for normal operation of the system is of 2milliseconds duration, followed by a 2 millisecond space pulse to formthe verify 1" verification signal to indicate to the transponder thatthe first data bit received by the interrogation station was a binary"l". The verify 1" signal is shown in waveform B of FIG. 3.

At the time that the NOR gate is driven to produce a high output, theoutput of the NOR gate 109 drops to a low output thereby enabling thefour stage binary counter 105 for operation.

Upon the application of the first high-to-low output transition from theastable multivibrator 74 to the trigger input of the bistablemultivibrator 77 0.5 milliseconds after the beginning of the verify 1mark pulse, a low-to-high trigger pulse is applied from the Q output ofthe multivibrator 77 through the differentiating circuit 97 to the NORgate 96 to drive the NOR gate 96 output low. This in turn causes theoutput of the enabled NOR gate 95 to become high, thereby resetting theflip-flop 95, 96.

Verification of the transmitted binary data from the transponder takesplace in conjunction with the operation of the verification NOR gates 88and 89, with the binary l stored in the final stage of the shiftregister 80 at this time enabling the NOR gate 88. A binary 0" stored inthe final stage of the shift register 80 enables the NOR gate 89. Asstated previously, both of these gates also are supplied with a lowenabling potential from the output of the NOR gate 84 in the transmitbistable multivibrator 83. Selected outputs from the counter 77, 78 areapplied to inputs of the NOR gates 88 and 89 to cause the inputs fromthe counter to be low during the time periods of 1.5 to 2.5 millisecondsfor the NOR gate 88, and 2.5 to 3.5 milliseconds for the NOR gate 89,respectively.

Thus, in the case of the binary l" which has been transmitted in theabove example, the NOR gate 88 is provided with low input signals to allof its inputs when the count of the counter 77, 78 reaches 1.5milliseconds and this condition lasts until 2.5 milliseconds after thestart of the mark pulse interval if not terminated sooner. As a result,a high output is obtained from the NOR gate 88, forcing the output ofthe NOR gate 90 to become low thereby enabling the NOR gate 92 duringthe 1.5 to 2.5 millisecond window." If the received verification signalis a verify 1", the mark output of the inverter 73 terminates at 2milliseconds, which is during this window when the NOR gate 88 providesa positive output. Termination of the received mark pulse causes a lowoutput to be obtained from the inverter 73 and this low output appliedto the other input of the NOR gate 92 forces its output to go high,resetting the bistable multivibrator consisting of the NOR gates 95 and96, with the output of the NOR gate 96 going high and the output of thegate 95 going low to produce the next shift pulse from the amplifier 98.

This shift pulse obtained from the output of the amplifier 98 also isapplied to the input of the counter to step the counter 105 from a countof 0 to a count of l, since the counter was released for operation whenthe output of the NOR gate 85 became high to place the transponder inthe transmit mode of operation. Stepping the counter 105 to a count of 1causes the Q output of the first stage of the counter to become low.This output is inverted and applied to one of the two inputs of a NORgate 117, forming one half of a bistable multivibrator with a second NORgate 118, to force the output of the NOR gate 117 to go low. Combiningthis low output with the low enabling input applied to the second inputof the NOR gate 118 from the now low output of the inverter 107 producesa low-to-high pulse transition at the output of the NOR gate 118. Thistransition is applied through a differentiating circuit 120 and an ORgate to the clear inputs of selected ones of the seven stages of theshift register 80, as

determined by the settings of a plurality of programmable switches 123.

The switches 123 may be variably set to store a unique addressidentifying the vehicle with which the transponder is associated. Sinceall of the stages of the shift register previously stored a binary 1,the clearing of selected ones of these stages permits any desiredpattern of binary signals to be stored in the register. The signalsapplied to the clear inputs of the stages of the register associatedwith closed switches 123 override the affect of the shift pulse appliedto the register 80.

With this operation, the second through eighth binary data bits of thetransponder message are stored in the register 80, with the second databit being present in the output stage.

If the second transponder data bit alsois a binary 1, as indicated inthe error free" waveform sequence in FIG. 4, the foregoing sequence forthe transmission and verification of the binary l is repeated. Theduration of the transmitted burst from the transponder is 2milliseconds, however, transmitted during the space interval of thefirst verify 1 sequence from the trackside interrogation station, asshown in solid lines in waveform E of FIG. 3. 7

If the next data bit of information shifted into the output stage of theshift register 80 is a space data bit, no longer are enabling signalsapplied to the NOR gates 88 and 125; but the Q output (binary of thefinal stage of the shift register 80 does enable the binary 0 checkinggate 89 and the transmit 0" timing NOR gate 127. The NOR gate 127provides a low output at this time however, because the Q output of thebistable multivibrator 78 is high due to the fact that the signaltransition causing the shift of information occured at 2 mi1- lisecondswhich is after the 1.5 millisecond time interval at which the Q outputof multivibrator 78 went high. As a result, both inputs to the NOR gate126 are low, causing a high output to be obtained therefrom, forcing theoutput of the NOR gate 111 to be low. Thus, no output is obtained fromthe transmitter driver 63 during the space pulse portion of the secondverify l signal.

By referring to FIG. 3 it may be seen that the verification signalstransmitted by the interrogation station each commence with a mark pulseinterval which is at least 2 milliseconds long (as in the case of theverified 1 signal shown in waveform B). Thus, immediately following theend of the space pulse portion of the second verify 1 signal sequence,the interrogation station commences transmitting a mark pulse,tentatively indicating a verify 0" signal. As a consequence, the outputof the transmit 0 timing NOR gate 127 is high for 1.5 milliseconds,causing a low output to be obtained from the NOR gate 126, which isinverted by the NOR gate 111 to a positive keying pulse applied to thetransmitter driver 63 to cause the transmission of a signal burst fromthe antenna 65. Since the signal burst is transmitted during a receivedmark interval, it is at a frequency of 189 kilohertz; and thistransmitted binary 0" from the vehicle transponder is illustrated inwaveform F of FIG. 3. The signal burst is terminated at 1.5 millisecondswhen the Q output of the bistable multivibrator 78 becomes high. Thus,the transmission of a binary 0 from the transponder always occurs duringthe mark pulse interval of the verify signal.

In the logic of the trackside or interrogation station receiver, thereceived 0" data bit is identified and causes a transmission of a verify0" signal back to the transponder unit. This signal has a 3 millisecondmark pulse followed by a 2 millisecond space pulse and is indicated inwaveform C of FIG. 3 and also is shown in the error free wavefonns ofFIG. 4. During the period between 2.5 and 3.5 milliseconds, the NOR gate89 provides a high output, forcing the output of the monitor NOR gate 90to be low thereby enabling the NOR gate 92 to check the receivedverification signal applied to the other input thereof. For a verify 0signal, the mark-to-space transition occurs at 3 milliseconds which iswithin the gating window provided by the output of the NOR gate 89. Ifamarkto-space transition occurs at this time, the NOR gate 92 produces ahigh output to trigger or reset the bistable mulnan-i tivibrator 95, 96to produce the next shift pulse to the shift register and to advance thecounter 105. This transmission and verification operation continues forthe duration of the transponder message, the length of which may bearbitrarily determined in accordance with the requirements of theparticular system with which the transponder and interrogation stationare used.

The high output from the NOR gate during the transmit mode of operationof the transponder is applied to one of the inputs of a NOR gate 163 toproduce a low output which is inverted by a NOR gate inverter 164 toproduce a high input to each of the NOR gates and 101, forcing theoutputs of these gates to go low. The inverter 102 causes a high inputto be applied to the S input of the input stage of the shift register 80to force the shift register 80 to be filled with binary l 1 8'.

In the transponder unit shown in FIG. 2, a 16 bit message istransmitted; and when the counter 105 reaches a count of 8, alow-to-high pulse transition is applied over a lead to a differentiatingcircuit 141. The differentiated positive pulse is applied to a firstinverter 143 which supplies a negative pulse to a pair of alann NORgates 144 and 145 the other inputs to which may be provided formonitoring alarm conditions such as high or low temperature conditionsin a refrigerator car or the like. The output of the NOR gates 144 and145 will depend upon the alarm condition, clearing the correspondingstage of the shift register 80 coupled with the output of the NOR gateto a 0 state if the alarm condition is present, or leaving thecorresponding stage of the shift register 80 set to a l state if thealarm condition does not exist.

As illustrated in FIG. 2, the last three stages of the shift register 80are provided with variable information in accordance with the settingsof three switches 147 which may be utilized to complete theidentification code of the vehicle, the first eight bits of which wereestablished by the settings of the switches 123 and the binary one inputcorresponding to the first address information bit required by thissystem. To produce the desired positive pulse applied to the switches147, the output of the NOR gate inverter 143 is again inverted by a NORgate inverter 148.

The foregoing operation of transmitting binary l or binary 0 inaccordance with the information stored in the shift register 80continues for the next 7 data bits of information stored in the register80. When the binary counter 105 reaches a count of 15, the binary I"loaded into the in-put stage with the first shift pulse following thesecond loading of the register reaches the output stage of the shiftregister 80 and constitutes the final or 16th data bit of the message.Other system formats could be employed which would not require thebinary 1" prefix and suffix.

When the counter 105 reaches a count of 16 a high-to-low pulsetransition appears on a lead 150 coupled to the output stage of thecounter 105, and is differentiated in a differentiating circuit 151 andapplied to a NOR gate 152, which normally is enabled by the low outputof the activity error NOR gate 114. This then causes a positive outputpulse to be ap plied from the NOR gate 152 to an end of transmissionbistable multivibrator 153, which is set to produce a positive inhibitoutput applied to the inhibit gate 71, blocking the output of theactivity check circuit 70 and turning off the operating power to thelogic circuit shown in FIG. 2. This then prevents a second transmissionof a successfully transmitted message from the transponder circuit. Whenthe transponder is moved out of the range of the interrogation station,the activity check circuit output drops and results in an activity off"pulse supplied over a lead 155 to the end-of-transmit bistablemultivibrator 153, resetting the bistable multivibrator to again enablethe inhibit gate 71. Thus, the next time the transponder is moved withinrange of a interrogation station the foregoing sequence of operation maybe repeated.

If at any time during transmission of the message, verifica tion ofa 1"pulse does not occur (error 1 of FIG. 4), a mark is present at theoutput of the inverter 73 for a period of greater than 2 milliseconds,permitting the stage 77 of the clock counter to be reset at 2.5milliseconds, thereby disabling the NOR gate 88 and preventing a resetpulse from appearing at the output of the NOR gate 92. For example,reference to waveforms C and D of FIG. 3 shows that a tracksideinterrogation station verify signal includes a 3 millisecond mark pulseinterval. Failure to receive any signal from the interrogation stationappears as a mark pulse interval of indefinite length. Occurence of anyof these mark pulse intervals following the transmission of a binary 1"from the transponder prevents proper verification and indicates areceived error. Similarly, a verify 0 error occurs if the mark pulseinterval in the verify signal is less than 2.5 milliseconds, or greaterthan 3.5 milliseconds, the window of gate 89.

In either such event, the output of the NOR gate 96 in the activitybistable multivibrator remains low, enabling the activity error NOR gate114. As a consequence, the next time that the bistable multivibrators 77and 78 in the clock counter are cleared, both of the other inputs to theNOR gate 114 become low, resulting in the output thereof going high.This output is applied through an integrating circuit 130 to the inputof the NOR gate 85 in the transmit bistable multivibrator 83.

The transmit bistable multivibrator 83 then is reset to its initialcondition of operation, with the output of the NOR gate 85 being low andthe output of the NOR gate 84 being high. This then terminatestransmission from the transponder and the initial mode of operation inresponse to received interrogation pulses occurs. It should be notedthat during this mode of operation, the NOR gates 88 and 89 aredisabled, as described previously, with only the interrogationmonitoring NOR gate 87 being enabled. As a consequence, reception ofverify 1" and verify 0 signal sequences of the type illustrated inwaveforms B and C of FIG. 3 has no affect on the circuit, since the gate87 causes shifting or stepping, of the register 80 in response only toproperly received interrogation pulses.

Upon receipt of such interrogation pulses, the register 80 continues tobe stepped as a maximum sequence counter from the count it attainedprior to the time the error was detected. It should be noted that thiscount is not necessarily the same as the count which originally wasstored in the register 80 to create the address for the vehicletransponder. This is of no consequence, however, since a random addresscode merely is utilized to prevent all of the vehicles fromsimultaneouslyattempting to respond and since the transponder messagesuniquely identify the vehicles from which they are sent.

Due to the fact that the initial address" for the vehicle is establishedby the random states attained by the different stages of the register 80upon the application of operating potential thereto, it is possible forall of the stages of the register 80 to assume a 0" state. Thiscondition will prevent the register from operating as a maximum sequencecounter, so that it is desirable to recognize this condition and forcethe storage of a l in the input stage of the register 80 upon theapplication of the first shift pulse. This is accomplished by a pair ofNOR gates 160 and 161 coupled to the 0" or Q outputs of all the stagesof the shift register 80 to produce a high output only if all of thestages of the register 80 simultaneously store a "0." This high outputis applied through the NOR gate 163 to produce a low output which isinverted by the NOR gate inverter 164 to produce a high input to each ofthe NOR gates 100 and 101, forcing the outputs of these gates to go low.The inverter 102 coupled to the output of the NOR gate 100 causes a highinput to be applied to the 5" input of the input stage of the shiftregister 80, as described previously. The first shift pulse applied tothe register 80, then causes the storage of this l pulse, at which timethe output of the NOR gate 163 goes high under the control of the outputof the NOR gate 85 in the transmit bistable multivibrator 83.

Referring again to FIG. 1, the transmitted bursts of signals supplied bythe transponder unit of FIG. 2 are received on the antenna 27 of thereceiver circuit 26 in the interrogation sta- Qncu tion as describedpreviously. A relatively narrow bandwidth circuit may be employed in thereceiver 26, since the injection and input frequencies vary together,both under the control of the same master frequency oscillator 10located in the interrogation station.

In view of the fact that the signals transmitted from the transponderantenna 65 are in the form of bursts of transmitted frequency followedby an off or no transmission condition of the transponder unit, it isdesirable to compare the signal level of the signals received by thereceiver unit 26 during the transmission of the bursts of signals fromthe transponder with a signal level which exists in the presence ofnoise and in the absence of signals being transmitted by the transpondercircuit. To accomplish this, the output of the mixer circuit 25 isapplied through two amplifier circuits 30 and 32 with the output of theamplifier circuit being applied to the peak detector 31, as describedpreviously, and with the output of the amplifier 32 being applied to apeak detector 33, which in turn provides an output signal to a sampleand hold circuit which may be of any suitable configuration. Atpredetermined time intervals, established by the signal pattern, a pulseis applied from the output of the data input and system logic circuit 1l to the sample and hold circuit 35 to cause it to be gated to store thesignal level present at the output of the peak detector 33 at that time.The timing of this gating pulse may be established in conjunction withthe timing provided by the data clock to the data input and system logic11 to occur at a time in the signal format when the output of thetransponder is known to be off between transmission of bursts of signalsfrom the transponder. The output of the sample and hold circuit 35 thenestablished a DC reference level for a differential amplifier comparisoncircuit 37 and is applied to the reference input of the differentialamplifier 37. This output also may be used as an AGC signal to controlthe gain of the input amplifier 28.

When a signal is transmitted from the antenna 65 of the transponder andis received by the receiver 26, the signal level thereof is applied bythe peak detector 31 to the differential amplifier circuit 37 where itis compared with the reference level provided by the circuit 35. If asignal burst is present, the output of the differential amplifierchanges from a normally high output to a low output to enable a pair ofNOR gates 39 and 40 which are utilized to decode the 0" and l receivedinformation, respectively.

To generate verification patterns, the signal transitions in the datainput and system logic signal applied to the input of the masterfrequency oscillator 10 to shift the frequency thereof are detected in astrobe circuit 41, with the signal transition signifying the beginningof a transmitted mark interval being applied to the 0" output of thestrobe circuit 41 in the form of a negative-going pulse during the first1.5 milliseconds of mark transmission. This pulse applied to the NORgate 39 produces a positive going output, signifying a received 0" ifthe NOR gate 39 is enabled by the output of the differential amplifier37 at the time the 0" strobe occurs. As stated previously, a 0" pulsetransmitted from the transponder always is transmitted during thebeginning of the transmission of a mark" pulse from the interrogationstation; so that strobing the gate 39 at this time provides anindication as to whether or not a 0 is being transmitted by thetransponder.

The strobe circuit 41 also provides a delayed 1 strobe pulse in responseto a signal transition applied to the input of the master frequencyoscillator 10 signifying a mark-to-space transition in the interrogationstation transmitted signal. The NOR gate 40 then is strobed in the samemanner as the NOR gate 39 but during the transmission of space" from theinterrogation station. If a l is being received at the same time (sincetransponder 1s" are transmitted during a received space in thetransponder), the output of the NOR gate 40 is a positive pulse upon theapplication of the strobe 1 pulse from the circuit 41.

The received pulse sequence, as determined by the outputs of the NORgates 39 and 40, may be supplied to a suitable utilization device 45,such as a printer, cathode ray tube display, or the like. The samesignals obtained from the outputs of the NOR gates 39 and 40 are appliedto the data input system logic 11 to control the transmitted pattern ofthe frequency shifts of the frequency of the master oscillator 10 forforming the verification signal patterns.

Refer now to FIGS. and 6, which show the details of the data input andsystem logic 11 and the utilization device 45 shown in FIG. 1, for amore complete understanding of the operation of the interrogationstation.

The nonnal mode of operation for the interrogation station in theabsence of any reply from a transponder is for the interrogation stationto continuously transmit the sequence of interrogation pulsesillustrated in waveform A of FIG. 3. In the interrogation station logiccircuit shown in FIG. 5, the basic timing for the operation of theinterrogation station to produce the different output waveformsillustrated in waveforms A, B, C, and D of FIG. 3 is controlled by afour stage shift register 200, operated as a timing control circuit.When power is first applied to the interrogation station logic orfollowing a manual clear operatioma low clear pulse isapplied to aterminal 201 and to the clear trigger inputs of all of the stages of theregister 200 to clear the register, causing the Q outputs thereof tobecome low and the outputs to become high. This same clear pulse also isshown in FIG. 5 as being applied to a terminal 204, located at the righthand side of the drawing, and is applied to a clear control NAND gate205 forcing the output of the NAND gate 205 to become high. This outputis inverted by a NOR gate inverter 206 to apply a low clearing pulse toa bistable multivibrator 207, causing the Q output of the miltivibrator207 to go low and the 6 output thereof to go high. At the same time, thelow clear pulse from the inverter 206 is applied to one of the inputs ofa NAND gate 209, forming a received message bistable multivibrator witha second NAND gate 210, causing the output of the NAND gate 209 to gohigh. The output of the NAND gate 210 is held low since both inputs toit, from the 6 output of multivibrator 207 and the output of NAND gate209 are high. This is the reset condition of the multivibrator 209, 210awaiting reception of a message from a transponder.

The clear pulse supplied to the terminals 201 and 204 is of relativelyshort duration and establishes the initial or starting condition ofoperation of the interrogation station. Upon termination of this pulse,the potential on the terminals 201 and 204 rises to a high potential,enabling the NAND gate 205 and enabling the NAND gate 214, the otherinput to which is obtained from the counter 21 (FIG. 1) providing theclock pulses used to coordinate the operation of the interrogationstation with the master frequency oscillator 10. The clock pulsesapplied to the terminal 21 occur at approximately a one kilohertz rateand appear as substantially a square wave signal indicated in waveform215. These pulses are applied directly to a timing NOR gate 217 and atiming NAND gate 218 and are inverted by the NAND gate 214 and appliedas short pulses to the register 200 and as clock pulses to a NOR gate222. When the second stage of the shift register counter 200 is cleared,the Q output thereof goes low and forces the output of the NAND gate 218to be held high until a binary 1" is stored in the second stage of thecounter 200.

Upon the initial clearing of the register counter 200, causing the Ooutputs to become high and the Q outputs to become low, the three inputssupplied to a NAND gate 220 from the 6 outputs of the first three stagesof the register all are high, as is an input applied thereto from a NANDgate 221, one of the inputs of which is the 0 output of the final stageof the register 200 forcing the output of the gate 221 to be high. Thiscoincidence of four high inputs to the NAND gate 220 causes its outputto be low at the start of operation of the circuit, thereby enabling theNOR gates 217 and 222 for the passage of clock pulses applied thereto.At the same time, the output of the NAND gate 220 is inverted by asingle input NOR gate 224, the output of which is applied to the l inputof the first stage of the shift register 200 to cause the insertion of al" timing signal into the register upon receipt of the first high-tolowtrigger pulse or shift pulse by the register 200.

For the purposes of illustration, assume that power is applied to thecircuit shown in FIG. 5 and that the clear pulse has terminated justprior to the To time interval of the clock pulse sequence 215 obtainedfrom the counter 21. As a consequence, when the initial low to highpulse transition occurs, the output of the NAND gate 214 drops from highto low to provide a negative trigger or shift pulse to the stages of theshift register 200, causing the storage of the "1 timing bit in thefirst stage of the register 200. This then produces a high output fromthe Q output of the first stage of the register 200.

At the same time, the output of the NAND gate 220 becomes high, due tothe removal of the enabling input obtained from the 6 output of thefirst stage of the counter register 200. This high output then forcesthe output of the NOR gate 217 to be driven low and causes the outputsof both NOR gates 217 and 222 to be held low so long as the output ofthe NAND'gate 220 remains high. The output of the NOR gate 222previously has been driven low by the output of the NAND gate 214,delayed by a delay circuit 219 which causes a loading or trigger pulseto be supplied to a received data multivibrator 224. This first lowoutput pulse from the NOR gate 222 operates as a trigger pulse on areceived data multivibrator 224 the inputs to which are the normal andinverted output of a control NAND gate 225, one input to which isobtained from the output of the NOR gate 40 (FIG. 1) and the other inputto which is a normally high input obtained from a storage overflow gateto be described subsequently. At this time, the output from the NOR gate40 is low since it has been assumed that no data is being received froma transponder unit. Thus, the output of the NAND gate 225 is high, beinginverted and applied to the binary l input of the bistable multivibrator224 by an inverted NOR gate 227, and being applied directly to the 0input; so that upon receipt of the trigger pulse from the NOR gate 222,the multivibrator 224 stores a 0" condition causing the 6 output toremain high and a Q output to remain low.

Shortly thereafter, the negative going or high-to-low pulse transitionat the output of the NOR gate 217 is applied through a differentiatingcircuit 229 to the trigger input of the bistable multivibrator 207 thesignal inputs to which are obtained from the Q and O outputs of themultivibrator 224. Due to the fact that the 6 outputs of themultivibrator 224 is high at this time, this first trigger pulsesupplied to the multivibrator 207 does not change its state.

At time 0 of the clock signal 215 when the 6 output of the fust stage ofthe register counter 200 goes low, this output is applied to one of fourinputs of an output transmitter control NAND gate 230, forcing theoutput of the NAND gate 230 to go high. This output is applied as thefrequency control signal to the master frequency oscillator 10 (F IG. 1)causing the frequency of the master frequency oscillator 10 to beshifted to the mark" output frequency. This condition of operation isalways attained whenever the output of the NAND gate 230 is high, and ahigh output is obtained from the NAND gate 230 any time any one of theinputs thereto is low. Thus for the time interval from 0 to lmillisecond, when the next high-to-low trigger pulse is applied to theregister counter 200 the output of the NAN D gate 230 is high. At 1millisecond a 0 is stored in the first stage of the counter register 200due to the high output of the NAND gate 220 applied to the 0 priminginput of the first stage of the register. This causes the 6 output ofthe first stage once again to go high so that output of the NAND gate230 once again becomes low, since all of the inputs applied thereto arehigh. This first l millisecond high output applied to the transmittermaster frequency oscillator 10 constitutes the one millisecond markpulse at the beginning of an interrogation pulse sequence or cycle asshown in waveform A of FIG. 3. When the output of the NAND gate 230 islow, the oscillator 10 transmits at a lower frequency corresponding tothe space portion of the sequence.

When the clock pulse at the output of the NAND gate 214 occurs at 3milliseconds, the binary I originally stored in the first stage of theregister has been moved through the register 200 to be stored in thelast stage. The first three stages of the register 200 then once againall store a binary O," causing a high input to be applied to the threeinputs of the NAND gate 220 connected to the O outputs of these firstthree stages. Storage of a binary l in the final stage of the registercounter 200 causes the Q output of that stage to go low forcing theoutput of a NAND gate 232, connected as half of a received 0" decodermultivibrator along with a NAND gate 233, to go high if themultivibrator 232, 233 already is not in this state of operation. Thecorresponding NAND gate 233 then produces a low output holding theoutput of the NAND gate 232 high.

The Q output of the final or fourth stage of the register counter 200goes high at 3 milliseconds enabling the NAND gate 221. At the sametime, a message recognition NAND gate 235 is provided with a highenabling input from the output of a 0" recognition NAND gate 237 on oneinput thereof, and with another high input from an error recognitionbistable multivibrator comprising a pair of NAND gates 240, and 241,with the NAND gate 241 being forced to produce a high output at thecommencement of operation of the circuit due to the application theretoof the low output of the NAND gate 220 at the start of operation. As aconsequence, the output of the NAND gate 235 is low forcing the outputof the NAND gate 221 to be high; so that at 3 milliseconds, the outputof the gate 220 once again becomes low, priming the 1" input to thefirst stage of the register counter 200.

When the trigger pulse next occurs at 4 milliseconds, the first stage ofthe counter 200 again stores a binary l, causing the NAND gate 230 onceagain to produce a high output signifying the commencement of the markportion of the next interrogation pulse. The foregoing cycle iscontinuously repeated, resulting in an interrogation sequence of lmillisecond mark pulses each followed by 3 millisecond space pulsesuntil a transponder station responds by transmitting data to theinterrogation station.

As described previously in conjunction with the operation of thetransponder shown in FIG. 2, the first data information transmitted by atransponder is a binary l which takes the form of a transmitted signalburst during the space interval immediately following any transmittedmark from the interrogation station.

Thus, during the space interval which follows the mark portion of aninterrogation pulse, the first mark transmission from the transpondershould be received during the space interval. At 3 milliseconds, asstated previously, the output of the NAND gate 220 goes low, thisoccuring one millisecond before the end of the interrogation pulse spaceinterval. This output is doubly inverted by the pair of NOR gateinverters 224 and 243 to generate a one millisecond low strobe pulseapplied to the NOR gate 40 shown in the receiver 26 of the interrogationstation (HO. 1).

If at this time a transmitted binary is being received, both inputs tothe NOR gate 40 are low, causing its output to become high. This outputapplied to the NAND gate 225, which already is enabled by the high inputfrom the storage overflow circuit, produces a l millisecond low outputfrom the NAND gate 225 which is inverted by the NOR gate 227 to cause ahigh enabling pulse to be applied to the l input of the multivibrator224. At this time, both inputs to the NOR gate 222 are low during thethree to 3.5 millisecond time interval causing a high output to beobtained therefrom. Upon the occurance of the next low-to-high pulsetransition at the output of the NAND gate 214 at 3.5 milliseconds(having no effect on the operation of the counter 200), the output ofthe NOR gate 222 produces a high-to-low trigger pulse which is appliedto the bistable multivibrator 224, causing the multivibrator 224 tostore the binary l received data signal. A binary 1 stored in themultivibrator 224 causes the Q output to be high and the Ooutput to below.

It should be noted that prior to this time the NOR gate 222 periodicallyproduced such trigger pulses, but these prior trigger pulses had noaffect on the operation of the multivibrator 224 since it wascontinuously primed with binary "0 priming signals.

At 4 milliseconds, the trigger pulse applied to the register 200 causesthe storage of the binary "1," obtained from the output of the NAND gate220, in the first stage of the register counter 200, as describedpreviously, thereby causing the output of the NAND gate 220 to becomehigh terminating the strobe input to the NOR gate 40 and terminating thesampling interval for the binary l received data.

Simultaneously with the storage of the binary l in the first stage ofthe register 200, a low-to-high pulse transition is applied from thedata clock divider 21 to the input of the NOR gate 217 causing ahigh-to-low pulse transition to appear at the output of the NOR gate217. This transition is differentiated in the differentiating circuit229 producing a trigger pulse to cause the binary information stored inthe bistable multivibrator 224 to be transferred into and stored in thebistable multivibrator 207, causing the Q output thereof to become highand the Q output to become low.

When this occurs, the NAND gate 210 of the received message bistablemultivibrator produces a high output, with the output of the NAND gate209 going low. This state of the multivibrator 209, 210 indicates that amessage is being received and this multivibrator remains set to thisstate until reset upon the termination of a message, application of aclear pulse, or upon an error indication. The high output from the NANDgate 210 is utilized to enable a pair of NAND gates 237 and 245corresponding, respectively, to the received 0" gate and a received lgate.

Since the first received information bit from the transponder is abinary l the other input to the NAND gate 245 is also high at this time,thereby causing the output of the NAND gate 245 to be low. This forces ahigh output from the NAND gate 237 which continues to enable the NANDgate 235 and forces the output of a 0" strobe NOR gate 247 to remainlow, this output being inverted by a single input NOR gate 248 toproduce a high input to the NOR gate 39, preventing sample for thepresence of a received signal during the initial portion of thecurrently transmitted mark pulse interval of a verify l signal sequencefrom the interrogation station.

Once the received message bistable multivibrator 209, 210 has beentriggered to the received message state, an additional NAND gate 249 isenabled by the output of the NAND gate 210, with the other input to theNAND gate 249 being obtained from the Q output of the second stage ofthe register counter 200. This insures that the transmitted mark fromthe interrogation station extends for at least two milliseconds, withthe time interval from 0 to 1 milliseconds being controlled through theNAND gate 230, as described previously for the generation of theinterrogation sequence, and with the Q output of the second stage of thecounter register 200 being high during the interval from 1 to 2milliseconds thereby producing a low output from the NAND gate 249 tohold the output of the NAND gate 230 high until the end of twomilliseconds.

Since the received 0" NOR gate 39 is not strobed during the markinterval of a verify l signal sequence, all of the inputs to theNANDgate 230 once again are high at 2 milliseconds, causing the output todrop low to produce the second half or space pulse portion of the verify1" signal shown in waveform B of FIG. 3. This corresponds to the firstR, signal shown in the normal error free transmission set of waveformsillustrated in FIG. 4. If during the space portion of this first verify1" sequence, a second binary "l" is being transmitted from a transponderunit, a signal is being received from the transponder during the spaceinterval of the verify l being transmitted from the interrogationstation. One millisecond prior to the end of this space interval thesampling of the received information in the NOR gate 40 again takesplace due to the change of state of the NAND gate 220, as describedpreviously, and the foregoing sequence is repeated.

Assume for the purposes of illustration that the third data bit to bereceived from a transponder is a binary "0. If this occurs, the entiresecond verify l mark and space sequence illustrated in the Error Free"set of FIG. 4 passes by without any transmitted data being received bythe trackside interrogation station. As a result, when the trigger pulsefrom the output of the NOR gate 222, occurs the output of the NAND gate225 is high, priming the bistable multivibrator 224 to receive a binary0. This causes the output of the multivibrator 224 to be low and theoutput to be high; and at 4 milliseconds, the trigger pulse obtainedfrom the output of the NOR gate 217 causes this information to be storedin the multivibrator 207, changing the state of the multivibrator 207.The change of state has not affect on the received message bistablemultivibrator 209, 210 but does force the output of the NAND gate 245 tobecome high. This high output applied to the input of the NAND gate 237coincides with the high input to the NAND gate 239 obtained from theoutput of the NAND gate 210 to produce a low output from the NAND gate237. A high output then is forced from the NAND gate 235, enabling theNAND gate 221 to extend the resetting of the NAND gate 220 to themillisecond clock pulse transition.

At the same time, the 0 strobe NOR gate 247 is enabled by the low outputof the NAND gate 237, which otherwise causes the output of the NOR gate247 always to be low, which, upon inversion by the inverter NOR gate248, produces a continuous high output to the NOR gate 39 preventing thesampling of .input signals applied to the NOR gate 39 in FIG. 1. Withthis low enabling input applied to the NOR gate 247, however, thetrigger or stepping pulse applied to the register counter 200 at lmillisecond causes the l to be moved from the first stage to the secondstage for the time period between 1 and 2 milliseconds. As a result, alow output is obtained from the Q output of the second stage producinglow inputs at both of the inputs of the NOR gate 247; so that the outputrises to a high level, inverted to a low level by the NOR gate 248,causing the 0" sample strobe to occur during the time period of l to 2milliseconds. Since a received 0 always occurs during the first 1.5milliseconds of a mark transmitted from the interrogation station, the0" sample strobe is timed to coincide with a received 0 if one is beingreceived.

Receipt of a binary 0 when the NOR gate 39 is strobed results in theoutput of the NOR gate 39 rising to a high level, inverted in a NOR gate250, to produce a high-to-low pulse which applied to the NAND gate 233in the received 0" bistable multivibrator forces the output of the NANDgate 233 to become high. This high output is applied to one of the twoinputs of the NAND gate 232, the other input to which is the high 6output of the final stage of the register counter 200, so that theoutput of the NAND gate 232 drops from a high to a low value, forcing ahigh output to be obtained from a received "0" identification NAND gate252. This high output is applied to one of the two inputs of the NANDgate 240 in the error bistable multivibrator thereby maintaining theoutput of the NAND gate 240 low, causing the output of the NAND gate 241to remain high.

At the same time, the high output obtained from the NAND gate 235enables a received zero control NAND gate 254, the other input to whichis the Q output of the third stage of the register counter 200. Thus, asstated previously the output NAND gate 230 produces a high output forthe first 2 milliseconds of each transmitted pulse interval so long asthe received message NAND gate 209, 210 is set to indicate that amessage is being received. When a binary 0" is identified, the storageof the 1" in the third stage of the register counter 200 causes the Qoutput of that stage to become high, which, combined with the high inputobtained from the NAND gate 235 produces a low output from the NAND gate254 holding the output of the NAND gate 230 high during the timeinterval from 2 to 3 milliseconds thereby extending the generation ofthe mark pulse interval portion to that of the verify 0" waveform C ofFIG. 3, and as indicated for the third verification pulse interval inthe normal Error Free set of waveforms illustrated in FIG. 4.

At the timing pulse occuring at 3 milliseconds, which steps the binary 1into the fourth stage of the register counter 200, all of the inputs tothe NAND gate 230 once again become high causing the output to becomelow to initiate the transmission of the space interval portion of theverify 0" signal. The NAND gate 220, however, is not enabled at this 3milliseconds timing pulse due to the fact that the NAND gate 221 has ahigh enabling signal applied thereto from the output of the NAND gate235. This output combines with the high output obtained from the 0output of the last stage of the register counter 200 during the timeperiod from 3 to 4 milliseconds to cause the output of the NAND gate 220to remain high until 4 milliseconds. At this time, the 4 millisecondtiming and shift pulse clears the register 200, causing the output ofthe NAND gate 221 then to become high to produce low output from theNAND gate 220 during the time interval from 4 to 5 milliseconds. As aconsequence, it may be seen that the trackside interrogation stationverify 0" signal sequence is a 5 milliseconds in duration as comparedwith the verify 1" signal sequence which is 4 milliseconds in duration.

As soon as the output of the NAND gate 220 goes low, the strobe 1"signal is obtained from the output of the NOR gate 243, with theinterrogation station logic system looking for the presence oftransmitted binary l information from a trans ponder during the lastmillisecond of the verify 0 signal interval. If a received transpondersignal is present at this time, the operation of the circuit asdescribed previously for reception of a binary 1" takes place. If nosignal is detected during this space interval, the system tentativelyagain identifies the absence of the signal as a binary O," withverification taking place during the first portion of the succeedingcycle of operation of the register counter 200.

The foregoing operation continues for the duration of received messagesfrom a transponder to identify the received data bits and to generatethe corresponding verification signal sequences supplied to thetransponder.

In order to utilize the received signals, a utilization device such as aprinter, cathode ray tube display, or the like must be employed. Due tothe fact that the signals received from the transponders occur at a veryhigh rate it is necessary to provide a buffer memory between thetrackside data logic shown in FIG. 5 and the printer or otherutilization device which ultimately responds to the received messages toreproduce them in a usable form. A circuit providing such a bufferstorage is shown in FIG. 6.

Initially when a power is applied to the logic shown in FIG. 5 it alsois applied to the buffer storage circuit shown in FIG. 6, which includesa time delay circuit 300, responsive to the application of operatingpower to the system for delaying the application of a high enablingsignal to a data input NAND gate 301, a load clock NAND gate 302, and anerror clock NAND gate 303 and a low (inverted) enabling signal to aregister full NOR gate 336 to prevent spurious operation of the bufferstorage circuitry until the logic circuit shown in FIG. 5 has beencleared for initial operation as described previously. At the same timethat power is applied to the time delay circuit 300, it also is appliedas a reset pulse to the reset input of a six stage binary or ringcounter 304 to set the counter to a count corresponding to a first oneof six l6-stage shift register storage circuits 307 to 312,respectively.

The six stage counter 304 provides a high output corresponding to theselected shift register with the remaining outputs being low and thecounter 304 operates sequentially in response to the application ofstepping pulses applied to an input terminal 315 upon the completion ofthe storage of a message in one of the shift registers 307 to 312.

Initially assume that the first stage of the counter 304 is enabledcausing a high output to be obtained from that stage and applied to theB input of the l6-stage shift register 307 and to a pair of NAND gates319 and 320, enabling these NAND gates.

The Q output of the bistable multivibrator 224 (FIG. 5) provides theserial data input to the buffer register circuit and is connected to theother input of the normally enabled input NAND gate 301. Received binaryl signals are in the form of high input pulses from the multivibrator224 and received binary signals are in the form of low input pulses. Ifthe binary l" signal condition is being received, the NAND gate 301produces a low output which is inverted by a NOR gate inverter 322 toproduce a high or enabling signal to the l or A inputs of all of thebufier storage registers 307 to 312. This information, however, cannotbe loaded into the shift register 307 until a trigger or shift pulse isapplied to the register.

The necessary shift pulses are in the form of load clock pulses obtainedfrom the Q output of the first stage of the register counter 200 (HO.and are high pulses lasting for the time interval from 0 to 1milliseconds in the operation of the register counter 200. These highpulses applied to the input of the NAND gate 302 produce a low outputfrom the NAND gate 302, which in turn is coupled to one of two inputs ofanother NAND gate 326, the other input to which is obtained from theoutput of the NAND gate 306 which normally is high due to the fact thatthe output of the NAND gate 303 normally is low.

As a consequence, each time that a load clock pulse is received at theinput of the NAND gate 302, a low-to-high pulse transition is obtainedfrom the output of the NAND gate 326 and is applied to the other inputof the NAND gate 319. This produces a high-to-low output pulse from theNAND gate 319 which is applied to the input of a clock pulse NAND gate329 to produce a low-to-high pulse transition. This transition isinverted by a single input NOR gate inverter 330, as a highto-lowtrigger or stepping pulse for the shift register 307.

Due to the fact that the B or 0" input to the shift register 307 isconstantly primed from the output of the counter 304 for the duration ofthe time that the counter 304 is set to its first stage of operation,whenever the output of the NAND gate 332 is low, indicating tentativeidentification of a received 0", a 0 is stored in the input stage of theshift register 307, On the other hand when a binary 1" is beingreceived, both the A and B inputs of the first stage of the shiftregister are primed by high inputs, and the parameters of the registerare selected such that this causes the storage of a binary l in theinput stage of the register when the load clock shift pulse is applied.

The serial data stream present at the output of the bistablemultivibrator 224 is stored in the shift register 307, upon theapplication of the load clock pulses to the input of the NAND gate 302,until the first binary 1" (which is the first transmitted pulse receivedby the interrogation station since the transponder always initiatestransmission with a binary l") reaches the final or 16th stage of theshift register 307. This stage is identified in FIG. 6 as the tag"stage, and a binary 1" stored in this stage causes a high output to beobtained therefrom. This high output applied to the other input of thealready enabled NAND gate 320 causes the output of the NAND gate 320 togo low, forcing the output of a three input register monitor NAND gate332 to go high. This high output is applied to a normally enabled NORgate 334 to cause the output of the NOR gate 334 to drop from a high toa low value, which is applied to the other input of the NOR gate 336,producing a high output from the NOR gate 336 indicative that a completemessage has been loaded in the register 307 and that the register isfull.

The output from the NOR gate 336 is applied to one of two inputs of amessage complete comparison NAND gate 260 (HO. 5), the other input towhich is the output of the received l" NAND gate 245 after beinginverted by a single input NOR gate 261. In the message fonnat the lastdata bit transmitted by a transponder is selected to be a binary l sothat reception of this sixteenth bit as a binary 1 produces a highoutput from the NOR gate 261, enabling the NAND gate 260. Thus, when theoutput of the NOR 336 goes high, indicating that the loading of theshift register 307 is complete, the output of the NAND gate 260 drops toa low value causing the output of a NAND gate 263 to rise to a highvalue. The NAND gate 263 fonns one-half of a message completemultivibrator including a second NAND gate 264.

This high output of the NAND gate 263 is applied to one of two inputs ofthe NAND gate 264, the other of which is obtained from the Q output ofthe fourth stage of the counter register 200. Thus, at the threemillisecond time interval following the reception of this finaltransmitted binary l, the Q output of this final stage of the counterregister rises from a low to high value causing the output of the NANDgate 264 to drop to a low value.

This output is utilized in the NAND gate 205 to force the output of theNAND gate 205 to become high which is inverted in the NOR gate inverter206 to produce a low reset trigger pulse which clears the multivibrator207 to its 0" state. At the same time, the received messagemultivibrator 209, 210 is reset, with the output of the NAND gate 209being high and the output of the NAND gate 210 being low. This reset iscomparable to the initial reset previously described for initiation ofoperation upon the application of the clear pulse to the NAND gate 205.

The output of the NAND gate 264 also is applied as the stepping pulseinput to the six stage counter 304 at the terminal 315 to step thecounter 304 to its next stage, thereby removing the enabling inputs fromthe NAND gates 319 and 320 associated with the shifi register 307. Thesecond stage of the binary counter 304 then enables the operation of thebufier storage circuit shift register stage 308, which includes acorresponding set of gates 319, 320, 329 and 330 which have beendescribed in conjunction with the operation of the shift register stage307.

Operation of the system then continues to store successive messages insuccessive ones of the buffer storage shift registers 307 to 312 withthe counter 304 being stepped upon the filling of each register 307 to312 as determined by detection of a binary l in the tag stage of theshift registers. In this manner, the complete sixteen bit messages aresequentially stored in different ones of the registers 307 to 312.

It should be noted that upon the occurance of the 4 millisecond clockpulse, the Q output of the final stage of the register counter 200 (FIG.5) once again becomes low forcing the output of the NAND gate 264 tobecome high. This high output coincides with a high output from the NANDgate 260 which is produced by the stepping of the counter 304 to thenext buffer storage stage which then causes the output of the NOR gate336 to be low. As a consequence, the message complete multivibrator 263,264, is switched back to its original state of operation, with theoutput of the NAND gate 264 remaining high and the output of the NANDgate 263 being low, holding the NAND gate 264 high. This then enablesthe NAND gate 205 to respond to reset clear pulses or error pulsesapplied to the other two inputs thereof. So long as all three of theinputs to the NAND gate 205 are high, however, its output remains low,causing a high output to be obtained from the inverter 206 to enable thereceived message multivibrator 209, 210 to respond to the first receiveddata bit of the next received message.

The foregoing sequence of operation continues for filling the shiftregisters in each of the buffer storage circuits 307 to 312 as describedpreviously.

In order to utilize the information stored in the buffer storagecircuits 307 to 312 in a suitable utilization device such a printer 340,a register unload control circuit 341 and a second six stage counter 343are provided. When the power up reset pulse is applied to the six stagecounter 304 to set that counter to a count of 1, corresponding to thefirst register 307, the counter 343 is similarly reset to a count of 6,corresponding to the final register 312 of the buffer storage circuits.

Thus, the first stepping or advance pulse applied to the counter 343steps the counter from stage 6 to stage 1 whereas the first steppingpulse applied to the counter 304 steps the counter from stage 1 to stage2. As a consequence, it may be seen that the counter 343 is sequentiallystepped to follow the stepping of the counter 304; so that initiallycontrol of the operation of the shift register 307 is effected by thecounter 304 without interference from the output of the counter 343.

Assume that the first received message is stored in the register 307 andthe counter 304 is stepped to its second stage enabling the register 308for storage of the second message in the manner described previously. Ifat this time it is desired to supply the first message to the printer340, the register unload control circuit 341 produces a high advance orstepping pulse on a lead 345 to a NAND gate 346, which normally isenabled by a high input on its other input. This causes a high-to-lowpulse transition to appear at the output of the NAND gate 346 to stepthe counter 343 from stage 6 to stage 1.

When the counter 343 is stepped to stage 1, the output of stage 1 goeshigh and is applied over a lead 348 to enable a pair of NAND gates 350and 351 in the register stage 307. At this time it should be noted thatthe NAND gates 319 and 320 are disabled since the counter 304 has beenstepped to stage 2. The register unload control circuit 341 thenprovides transmit clock pulses over a lead 353 to the NAND gate 350 tocontrol the stepping or shifting of the information out of the shiftregister from the final stage through the now enabled NAND gate 351, aNAND gate 355, and NOR gate 357 to produce the binary serial train tothe register unload control circuit 341. The control circuit in turnsupplies the necessary signal format to the printer 340.

Thecontrol circuit 341 includes a counter for counting the number oftransmit clock pulses applied to the register 307; and when 16 clockpulses have been recorded, a stepping pulse is applied over the lead 345to the NAND gate 346 to step the counter 343 to the next register, withthe sequence then being repeated. It should be noted that NAND gates 350and 351 are provided in each of the buffer circuits 307 to 312 but areenergized for only a single buffer storage circuit stage at a time, withthe remaining stages being prevented from applying output signals to theregister unload control circuit 341.

It is apparent that erroneous operation of the storage and removal ofdata from the bufier storage circuits 307 to 312 would occur if anattempt were made simultaneously to store information in a storageregister and to obtain information from the register. To prevent thisfrom occuring, a pair of NAND gate comparison tree circuits 350 and 351are provided, with the circuit 350 providing a low output whenever thecounters 304 and 343 both are stepped to the same stage. For example, ifthe counters 304 and 343 both were stepped to stage 2, the bufferstorage circuits all would be full and an attempt then would be made bythe counter 304 to enable the storage circuit 308 from which informationwas presently being removed, for the reception of new data. When thisoccurs, the high output from the NAND gate tree 350 is inverted by a NORgate inverter 350A and is applied to the input of the clock NAND gate302 forcing the output thereof to go high, which in turn results in alow output from the NAND gate 326 thereby disabling the application ofthe clock signals to any of the buffer storage circuits 307 to 312 fromthe logic circuit shown in FIG. 5.

At the same time, the low output of the inverter 350A is applied to thestorage overflow input of the input NAND gate 225, (FIG. 5) to renderthe NAND gate 225 insensitive to input signals and forcing its output togo high, indicative of a continuous received binary 0" signal. This inturn forces an error in the logic, which is transmitted to the vehicleattempting to supply data to the interrogation circuit to cause aresetting of the transponder for a subsequent attempt at transmission tothe trackside interrogation unit. As soon as the counter 343 is steppedto the next stage, however, the inverted output of the NAND gate tree350 rises to a high value, permitting resumption of the normal operationof the circuit by removing the inhibiting signals from the NAND gates302 and 225.

Similarly, it is desired to prevent the register unload control circuit341 from initiating the removal of information from a buffer storagecircuit 307 to 312 when the storage circuit is empty. This isaccomplished by the NAND gate tree 351,

limit] which compares each of the outputs of the six stage counter 304with the next preceeding corresponding output of the counter 343 toproduce a low output from a NOR gate inverter 351A. This output isapplied to the input of the NAND gate 346, forcing its output to go highto prevent further stepping of the counter 343.

For example if the counter 304 is set to stage 2, corresponding to anattempt to supply information to the buffer storage circuit 308, thecounter 304 remains set to this stage continuously permitting theapplication of input data to the register 308 until a tag binary l pulsereaches the sixteenth stage of the register 308. Until this occurs, nofurther stepping of the six stage counter 304 takes place. If, in themeantime, the register unload control pulse applied over the lead 345through the NAND gate 346 steps the counter 343 from stage 6 to stage 1to permit the removal of information from the register 307, coincidenceof this output of stage 1 of the counter 343 with the output of thesecond stage of the counter 304 produces a low output from the NAND gatetree circuit inverter 351A. This output then inhibits the passage offurther stepping pulses through the NAND gate 346. Thus, the counter 343cannot be stepped from stage 1 to stage 2 so long as the second bufferstorage circuit 308 is being controlled by the input 304.

The foregoing describes the manner in which the system at theinterrogation station performs for error-free operation to produce asequence of signals as indicated in the Error Free set shown in FIG. 4.Previously, the operation of the transponder upon receipt of incorrectverification signals has been described and the manner of operation ofthe circuit logic shown in FIG. 5 upon detection of an error now will bedescribed.

As stated previously, when a binary 0 data bit is to be transmitted, thetransponder in the vehicle does not transmit any information during thetime that a binary I would have been transmitted during the transmissionof a space interval following any markinterval from the interrogationstation. At the interrogation station, the lack of reception of a binaryl during the space interval is tentatively identified as a binary 0"which will be transmitted during the next mark transmission from theinterrogation station. This causes the interrogation station, throughthe operation of the NAND gate 237 and NAND gate 254 to commencetransmission of a verify 0" signal sequence, commencing with a threemillisecond mark interval.

Thus, during normal reception of a received 0" signal the output of theNAND gate 232 is low during the period from 1 millisecond, marking thebeginning of the received 0 low output from the NOR gate 250, until 3milliseconds when the Q output of the final stage of the counterregister 200 becomes low, forcing the output of the NAND gate 232 to behigh. As a consequence, the output of the NAND gate 252 remains high forthis first three millisecond interval to prevent setting of the errorbistable including the NAND gates 240 and 241. In the event, however,that no received 0" signal is decoded in the NOR gate 39 (FIG. 1), theNAND gate 233 remains in a low output condition for the time intervalfrom 1 to 3 milliseconds, with the NAND gate 232 producing a high outputthroughout this time interval. As a consequence, when the counterregister 200 is stepped to store the l in the third stage at the lmillisecond interval, all three inputs to the NAND gate 252 are high,causing a low output pulse to be obtained therefrom. This pulse, appliedto the input of the NAND gate 240 in the error bistable circuit 240, 241forces the output of the NAND gate 240 to be high at the 2 millisecondtime interval. This output coincides with the other high input appliedto the input of the NAND gate 241 to cause the output of the NAND gateto go low at the 2 millisecond interval.

The low output of the NAND gate 241 is applied to the input of the NANDgate 303 in the storage register circuit shown in FIG. 6 to force theoutput of the NAND gate 303 to be high, enabling the NAND gate 306 topass high frequency clock pulses from a suitable source such as a pointon the frequency divider chain of FIG. 1 (these clock pulses for examplemay be 64 kilohertz in frequency). These pulses then are applied throughthe NAND gate 326 to the register in which the message is being storedto rapidly clear the register to store all information.

At the same time, this low output at 2 milliseconds from the bistablemultivibrator 241 is applied to the input of the NAND gate 230 (FIG. tomaintain the output of the NAND gate 230 high until the error bistable240, 241 is reset. This does not occur until the output of the NAND gate220 goes low at four milliseconds, thereby causing the transmission ofan error signal of the type shown in waveform D of FIG. 3 and asindicated as error" in the various waveforms shown in FIG. 4. Theresponse of the vehicle transponder to an error signal is the same,irrespective of the manner in which the error was caused, since thevehicle transponder fails to see a mark-tospace transition during eitherthe verify 1" or verify 0" intervals in the transponder comparisoncircuit. As stated previously, this causes the transponder to revert toa mode in which it commences counting received interrogation pulses fromthe interrogation station.

It further should be noted that, in the interrogation station, the errorpulse obtained from the output of the NAND gate 241 also is appliedthrough the NAND gate 205 and NOR gate 206 to reset the bistable 207 andthe received message bistable 207; so that the interrogation stationreverts to its interrogation transmit mode of operation.

In summary, it is possible to obtain an error in thetransponder/verification signal sequence in any one of four differentways which are identified in FIG. 4 by the sets of waveforms labeledError 1" through Error 4". In Error l", the vehicle transmits a binary1" but does not receive the verify 1". In the vehicle transponderfurther transmission is terminated due to the non verification of thetransmitted binary 1". The trackside interrogation station identifiesthis as a tentative transmitted binary 0" and responds by transmitting averify 0. Since no binary 0," however, is received, the transmittercontinues the duration of the mark interval to form the error signal ofwaveform D in FIG. 3. Following this, the trackside interrogationstation reverts to the transmission of the interrogation signalsequence.

The second error possibility (Error 2 of FIG. 4) is when a binary 0" isbeing transmitted and the vehicle misses the verify 0" signal for somereason. The vehicle then ceases transmission since it did not receivethe verify 0", and the transmitter identifies a tentative 0" as in theprevious example. Again, as in the previous example, the tracksideinterrogation station reverts to the error mode followed by theinterrogation mode of operation as described in conjunction with theexample for error 1.

A third type of error (Error 3 of FIG. 4) which may occur is when abinary l is transmitted but is missed by the interrogation stationreceiver. At the interrogation station this is identified as a tentative0 and a verify 0 is transmitted. Since the mark-to-space transition,however, does not occur during the binary l window being utilized forcomparison in the transponder, no verification takes place and thevehicle ceases transmission. This is identified in the interrogationstation as a tentative received Since no 0 in fact is received, thesignal is extended to an error signal followed by the reversion of theinterrogation station transmitter to the interrogation mode ofoperation.

The fourth type of error which can occur (Error 4 of FIG. 4) is when abinary 0" is being transmitted by a transponder and is missed at theinterrogation receiver. At the interrogation station a tentative 0" isidentified and a verify 0" sequence commences. Since the received binary0" is not detected at the interrogation station, however, theverification signal is extended to an error signal; and the transmitterat the interrogation station reverts to the interrogation mode ofoperation. At the vehicle, no verification of the transmitted 0 data bittakes a place; so that the vehicle ceases transmission again revertingto a mode of counting the interrogation pulses followed by reinitiationof transmission as described previously.

It further is possible, because of the random address provided by theshift register counters in the vehicle transponders, that two or morevehicle units may initiate transmission at the same time. If phasecancellation of the signals takes place, the trackside interrogationstation continues to transmit the interrogation pulses and the vehicleunits fail to obtain verification and revert the interrogation receptionmode. If the signals do not phase cancel, however, a verify l istransmitted by the trackside interrogation station and is used in eachof the vehicles to verify that the first transmitted binary l wasproperly received in the interrogation station receiver. In the sequenceof operation which has been described previously, however, it should benoted that the binary l transmitted from a vehicle transponder is transmitted prior to the time that a binary 0 is transmitted for the same bitposition. As a consequence, since the binary 1" for any bit position issent first, a verify 1 is transmitted by the trackside interrogationstation. As a result the vehicle transponder which transmits a binary lreceives proper verification and proceeds with transmission but thevehicle transponder which transmits the first binary 0", in a bitposition in which the other transponder transmits a binary "1, fails toreceive verification and resets as in the case of the "Error 2 which hasbeen described above. This operation is illustrated in FIG. 4 in the setof waveforms labeled Simultaneous vehicle transmission."

The message bits are always followed by a last binary l transmission bythe vehicle which can be programmed as described previously by causingthe first stage of the vehicle transponder shift register to be set tostore a binary l when the shift register 80 is reset for transmission ofthe second eight bits of infonnation from the transponder. This isnecessary since the last digit transmitted by the vehicle is onlypartially checked by the trackside interrogation station. As a resultall of the message bits then are provided with maximum error checkingsecurity.

In conjunction with the description of the operation of FIG. 1 it shouldbe noted that a noise strobe is supplied by the data input and systemlogic II to the sample and hold circuit 35 to establish the referencelevel for operation of the signal detection differential amplifier 37.In addition the input and system logic circuit 11 provides a dump signalto the amplifier 30 to reset the reference levels for the peak detectors31 and 33. These two signals are obtained from the interrogation stationlogic shown in FIG. 5 as follows:

A noise strobe NAND gate 270 is enabled by the high output of the NANDgate 237 following receipt of each binary I from the transponder andwhile in the interrogation mode, and is provided with a second highinput during the l to 2 millisecond interval from the Q output of thesecond stage of the register counter 200. Coincidence of these twoinputs causes the gate 237 to produce a I millisecond long low noisestrobe" pulse to the sample and hold circuit 35. It should be noted thatno noise strobe pulse is produced after receipt of a binary 0" since theoutput of the NAND gate 237 is low at the time the second stage of thecounter 200 provides the output to sample the gate 270.

The dump signal is provided during the receive message mode only, andfollowing a received I" the output of the NAND gate 245 is low, enablinga NOR gate 271. Two other inputs to the NOR gate 271 are provided, oneby the 6 output of the first stage of the register counter 200 and theother from the NAND gate 214. These both are low, causing a high outputto be applied from the NOR gate 271 to an output NOR gate 273, drivingthe output low. This condition remains until 0.5 milliseconds when theoutput of the NAND gate 214 again rises, causing the output of the NORgates 271 and 273 once again to become low and high, respectively.

Following receipt of a 0" the output of the NOR gate 271 remains low,enabling the NOR gate 273. A NOR gate 274 is enabled by the then lowoutput of the NAND gate 237; and

IOIOJ 001" during the time interval of 2.0 to 2.5 milliseconds, the 6output of the third stage of the register counter 200 and the output ofthe NAND gate 214, the other two inputs to the NOR gate 274 are low.Thus, a high input is supplied to the NOR gate 273 to produce a low dumppulse at its output during the 2.0 to 2.5 millisecond time interval.

I claim 1. A signalling system for identifying and monitoring atransponder unit including in combination:

a transponder unit including means normally in an initial condition fortransmitting a unique signal train upon receipt of a transmittedinterrogation signal;

an interrogation unit including means for generating and transmittingsaid interrogation signal and for receiving said unique signal train;

means in the interrogation unit responsive to reception of said uniquesignal train for terminating transmission of said interrogation signaland for initiating transmission of a verification signal traincorresponding to the received signal train;

means in the transponder unit for comparing the verification signaltrain with the transmitted unique signal train and producing an outputupon failure of verification;

means in the transponder unit for terminating transmission from and forresetting the means for transmitting the unique signal train in thetransponder unit to the initial condition in response tosaid output fromthe comparing means; and

means in the interrogation unit for causing the interrogation unit torevert to transmission of the interrogation signal upon termination oftransmission by the transponder unit.

2. The combination according to claim 1 wherein the verification signaltrain is transmitted simultaneously from the interrogation unit withtransmission of the unique signal train from the transponder unit.

3. The combination according to claim 1 further including meansresponsive to the received verification signal train for controlling theoperation of the means for transmitting the unique signal train from thetransponder unit.

4. The combination according to claim 1 further including utilizationcircuit means and means in the interrogation unit for decoding theunique signal train transmitted thereto from the transponder unit andforsupplying the decoded signal to utilization circuit means; andwherein the unique signal train is composed of signals of a plurality oftypes and the verification signal train is transmitted to thetransponder simultaneously with receipt of the unique signal train fromthe transponder, the verification signal sequence being in the form of apulse sequence of a different predetermined relationship forverification of received signals of each of said types.

5. The combination according to claim 4 wherein two types of signals aretransmitted by the transponder unit,.both types being in the form ofpulses of a predetermined type, the time of transmission of said pulseswith respect to the verification signal train being transmitted by theinterrogation unit determining which of the two types of signals isbeing transmitted by the transponder unit.

6. The combination according to claim 5 wherein the verification signalsequences are in the form of mark and space pulse sequences, and furtherincluding a shift register means for supplying the unique signal trainfrom the transponder, the shift register supplying signals of first andsecond types and wherein a signal of said one of said two typestransmitted by the transponder unit is generated in response to a firsttype of signal supplied by the shift register simultaneously with areceived space signal in the verification signal train and whereintransmission of a signal of said other of said two types from thetransponder unit is generated in response to a second type of signalsupplied by the shift register simultaneously with the receipt of a marksignal in the verification signal train from the interrogator unit.

7. The combination according to claim 6 further including meansresponsive to mark-to-space transitions in the received verificationsignal train for providing a sequence of shift pulses to the shiftregister to shift the same.

8. The combination according to claim 4 wherein the unique signal traincomprises a message having a predetermined number of bits of informationand the utilization circuit means includes a plurality of buffer storageregister means each having a capacity for storing at least one messagewith means for supplying the message at an input bit rate to theregister means for storage therein and further including outpututilization means operable at an output bit rate different from theinput bit rate at which the message is supplied to the register means,with means responsive to the storage of the message in a register meansfor enabling the output utilization means to remove the message from theregister at said output bit rate.

9. The combination according to claim 8 wherein the plurality ofregister means includes at'least two register means and furtherincluding means responsive to the filling of one of said register meansfor preventing the application of further information bits thereto andfor transferring the application of information bits to the other of theregister means first comparison means for sensing when all of saidplurality of registers have been filled with messages for preventing theapplication of further information bits to the register means, andsecond comparison means for sensing when all of the registers areemptied for preventing the output utilization means from removingfurther infonnation from said registers.

10. The combination according to claim 9 further including means forsequentially enabling the shift register means, wherein each registermeans has a capacity equal to the number of bits in each message, withfirst shift pulses for the shift register means being supplied to theshift registers at the input signal rate for storing data in the enabledshift register, with means for preventing the application of said firstshift pulses to a register means upon thefilling of the register meansand for transferring control of the shift register means to the outpututilization means, the output utilization means applying second shiftpulses to the register at said output bit rate.

11. A signalling system for identifying and monitoring a transponderunit with an interrogation station transmitting interrogation andverification signals, the system including in combination:

transmission means in said transponder unit operable upon receipt of atransmitted interrogation signal for generating and transmitting aunique signal from said transponder unit;

means in the interrogation station responsive to the signals received bythe interrogation station from the transponder unit for generating asequence of verification signals for verifying said received signals;means in the transponder unit for comparing received verificationsignals with the transmitted unique signal for producing an output uponfailure of verification; and

means for terminating transmission from the transponder unit and forresetting the transmission means of the transponder unit to an initialcondition in response to said output of the comparing means, causing thetransponder unit to be rendered responsive to a transmittedinterrogation signal for reinitiating transmission therefrom.

12. The combination according to claim 11 wherein the transponder unittransmits signals of first and second binary conditions and theverification signal sequence supplied by the interrogation stationincludes signal intervals of a first predetermined pattern for verifyingsaid first binary condition and signal intervals of a secondpredetermined pattern for verifying said second binary condition, thetransponder further including first clock circuit means enabled foroperation during one of the signal intervals of each of the receivedverification patterns, the comparing means including gate circuit meansresponsive to the received verification signal, the transponder signal,and the output of the first clock circuit means for producing saidoutput upon failure of verification.

muru

13. The combination according to claim 12 wherein the first and secondbinary conditions are binary l and binary 0," respectively and thesignal format of the verification signal is such that the verificationpattern for a binary l" received from the transponder unit is in theform of a mark pulse of a first predetermined length followed by a spacepulse of a first predetermined length and wherein the verificationpattern for a binary received from the transponder unit is in the formof a mark pulse of a second predetermined length followed by a spacepulse of a second predetermined length, the length of at least one ofthe mark or space pulses used for verifying a binary l being differentfrom the length of the corresponding mark or space pulses in theverification pattern for a binary O, with the gate circuit meansincluding first and second verifier gates, the first gate being enabledby a binary l from the transponder and the second gate being enabled bya binary 0" from the transponder, with pulses from the first clock meansbeing applied successively to the first and second verifier gates toproduce outputs therefrom coinciding with the expected mark-to-spacetransitions in the verification patterns, and means responsive to theverification signal and the outputs of the first and second verifiergates for producing said output upon failure of the mark-to-spacetransitions of the verification signal to occur during the time anoutput is present from the first or second verifier gate.

14. The combination according to claim 12 further including amulti-stage shift register in the transponder with further gate circuitmeans interconnecting the output and input ofthe shift register to causethe register to be operated as a maximum sequence counter; meansresponsive to the interrogation signals for supplying shift pulses tothe shift register; means responsive to a first predetermined codepattern stored in the shift register for enabling the transmissioninitiating means and for disabling the further gate means, permittingoperation of the register as a shift register means responsive tooperation of the transmission initiating means for storing apredetermined code pattern in the shift register corresponding to thesequence of first and second binary conditions to be transmitted fromsaid transponder, the output of the final stage of the shift registerproviding the transponder output, and means responsive to pulsetransitions in the received verification signal patterns for providingshift pulses for the shift register.

15. A transponder for use in a signalling system including aninterrogation station transmitting a sequence of interrogation signals,the transponder including in combination:

a multistage shift register means, having at least an input stage and anoutput stage, each stage of the shift register means capable of beingset to either first or second states of operation corresponding to twobinary conditions and the stages storing an initial sequence of binaryconditions upon initial energization;

means responsive to the interrogation signals for providing a sequenceof shift pulses to the shift register to shift the same;

means coupled with the input stage of the shift register for causing theshift register to be filled with a first predetermined pattern of binaryconditions in response to the application of shift pulses thereto;

means coupled with the shift register for sensing the storage of saidfirst predetermined pattern therein to produce a control signal;

means responsive to the control signal for supplying a secondpredetermined binary sequence for storage in the shift register; and

gate means responsive to the control signal and the output of the outputstage of the shift register for providing an output signal train fromthe transponder.

16. The combination according to claim 15 wherein the firstpredetermined pattern is all stages of the shift register set to saidfirst state of operation.

17. The combination according to claim 15 whereby the initial binarysequence established in the shift register upon inimun tial energizationis a random sequence and the means for causing the shift register to befilled with a first predetermined pattern of binary conditions includessecond gate means responsive to the output of the output stage of theshift register for causing the register to be operated as a maximumsequence counter, the second gate means being disabled in response tosaid control signal.

18. The combination according to claim 15 further including means fortransmitting said output signal train from the transponder and whereinthe interrogation station further transmits a sequence of signalsuniquely verifying signals received by the interrogation station fromthe transponder, the transponder further including means responsive tothe receipt of the verification signals for providing shift pulses tothe shift register.

19. A buffer storage circuit for temporarily storing messages in theform of a binary bit train of a predetermined length supplied to thebuffer storage circuit at one bit rate and removed from the bufferstorage circuit at a second bit rate including in combination:

a plurality of storage register means each having a capacity for storingat least one of said messages;

input control means for sequentially enabling the storage registers forthe receipt of an input message;

input load means responsive to enabling of a register by the inputcontrol means to cause the storage of information therein at the bitrate of an input message;

first means coupled with the storage register means and responsive tothe storage to capacity of a storage register means for causing theinput control means to enable the next register in the sequence for thereceipt of an input message;

register unload control means; and

second means coupled with the storage register means and responsive tothe storage to capacity of a register for enabling the register unloadcontrol means to remove the message from the register at said second bitrate.

20. The combination according to claim 19 further including inhibitingmeans responsive to the storage to capacity of all of said plurality ofregisters for inhibiting operation of the input load means.

21. The combination according to claim 20 wherein the second meansfurther senses completion of removal of a message from a register by theunload control means to enable the unload control means to remove amessage from the next filled register in the sequence.

22. The combination according to claim 21 wherein the input controlmeans includes a first counter means having a predetermined number ofoutputs corresponding to the number of register means and the secondmeans includes a second counter means having a predetermined number ofoutputs corresponding to the number of register means and advanced toenable removal of messages sequentially from the register means, andwherein the inhibiting means includes first gating means responsive tocorresponding outputs from the first and second counter means indicativethat information has not been removed from the register to which thefirst counting means has progressed for inhibiting operation of theinput load means and further includes second gating means responsive toa combination of outputs of the first and second counter means, with theoutput of the second counter means corresponding to the register justprior to the one in the sequence which is enabled by an output from thefirst counter means, for inhibiting operation of the register unloadcontrol means.

23. A dual mode register circuit including in combination:

a multistage shift register means having at least an input stage and anoutput stage, each stage of the shift register means capable of beingset to either first or second states corresponding to two binaryconditions. and the stages storing information in the form of an initialsequence of binary conditions upon initial energization thereof;

1. A signalling system for identifying and monitoring a transponder unitincluding in combination: a transponder unit including means normally inan initial condition for transmitting a unique signal train upon receiptof a transmitted interrogation signal; an interrogation unit includingmeans for generating and transmitting said interrogation signal and forreceiving said unique signal train; means in the interrogation unitresponsive to reception of said unique signal train for terminatingtransmission of said interrogation signal and for initiatingtransmission of a verification signal train corresponding to thereceived signal train; means in the transponder unit for comparing theverification signal train with the transmitted unique signal train andproducing an output upon failure of verification; means in thetransponder unit for terminating transmission from and for resetting themeans for transmitting the unique signal train in the transponder unitto the initial condition in response to said output from the comparingmeans; and means in the interrogation unit for causing the interrogationunit to revert to transmission of the interrogation signal upontermination of transmission by the transponder unit.
 2. The combinationaccording to claim 1 wherein the verification signal train istransmitted simultaneously from the interrogation unit with transmissionof the unique signal train from the transponder unit.
 3. The combinationaccording to claim 1 further including means responsive to the receivedverification signal train for controlling the operation of the means fortransmitting the unique signal train from the transponder unit.
 4. Thecombination according to claim 1 further including utilization circuitmeans and means in the interrogation unit for decoding the unique signaltrain transmitted thereto from the transponder unit and for supplyingthe decoded signal to utilization circuit means; and wherein the uniquesignal train is composed of signals of a plurality of types and theverification signal train is transmitted to the transpondersimultaneously with receipt of the unique signal train from thetransponder, the verification signal sequence being in the form of apulse sequence of a different predetermined relationship forverification of received signals of each of said types.
 5. Thecombination according to claim 4 wherein two types of signals aretransmitted by the transponder unit, both types being in the form ofpulses of a predetermined type, the time of transmission of said pulseswith respect to the verification signal train being transmitted by theinterrogation unit determining which of the two types of signals isbeing transmitted by the transponder unit.
 6. The combination accordingto claim 5 wherein the verification signal sequences are in the form ofmark and space pulse sequences, and further including a shift registermeans for supplying the unique signal train from the transponder, theshift register supplying signals of first and second tyPes and wherein asignal of said one of said two types transmitted by the transponder unitis generated in response to a first type of signal supplied by the shiftregister simultaneously with a received space signal in the verificationsignal train and wherein transmission of a signal of said other of saidtwo types from the transponder unit is generated in response to a secondtype of signal supplied by the shift register simultaneously with thereceipt of a mark signal in the verification signal train from theinterrogator unit.
 7. The combination according to claim 6 furtherincluding means responsive to mark-to-space transitions in the receivedverification signal train for providing a sequence of shift pulses tothe shift register to shift the same.
 8. The combination according toclaim 4 wherein the unique signal train comprises a message having apredetermined number of bits of information and the utilization circuitmeans includes a plurality of buffer storage register means each havinga capacity for storing at least one message with means for supplying themessage at an input bit rate to the register means for storage thereinand further including output utilization means operable at an output bitrate different from the input bit rate at which the message is suppliedto the register means, with means responsive to the storage of themessage in a register means for enabling the output utilization means toremove the message from the register at said output bit rate.
 9. Thecombination according to claim 8 wherein the plurality of register meansincludes at least two register means and further including meansresponsive to the filling of one of said register means for preventingthe application of further information bits thereto and for transferringthe application of information bits to the other of the register meansfirst comparison means for sensing when all of said plurality ofregisters have been filled with messages for preventing the applicationof further information bits to the register means, and second comparisonmeans for sensing when all of the registers are emptied for preventingthe output utilization means from removing further information from saidregisters.
 10. The combination according to claim 9 further includingmeans for sequentially enabling the shift register means, wherein eachregister means has a capacity equal to the number of bits in eachmessage, with first shift pulses for the shift register means beingsupplied to the shift registers at the input signal rate for storingdata in the enabled shift register, with means for preventing theapplication of said first shift pulses to a register means upon thefilling of the register means and for transferring control of the shiftregister means to the output utilization means, the output utilizationmeans applying second shift pulses to the register at said output bitrate.
 11. A signalling system for identifying and monitoring atransponder unit with an interrogation station transmittinginterrogation and verification signals, the system including incombination: transmission means in said transponder unit operable uponreceipt of a transmitted interrogation signal for generating andtransmitting a unique signal from said transponder unit; means in theinterrogation station responsive to the signals received by theinterrogation station from the transponder unit for generating asequence of verification signals for verifying said received signals;means in the transponder unit for comparing received verificationsignals with the transmitted unique signal for producing an output uponfailure of verification; and means for terminating transmission from thetransponder unit and for resetting the transmission means of thetransponder unit to an initial condition in response to said output ofthe comparing means, causing the transponder unit to be renderedresponsive to a transmitted interrogation signal for reinitiatingtransmission therefrom.
 12. The coMbination according to claim 11wherein the transponder unit transmits signals of first and secondbinary conditions and the verification signal sequence supplied by theinterrogation station includes signal intervals of a first predeterminedpattern for verifying said first binary condition and signal intervalsof a second predetermined pattern for verifying said second binarycondition, the transponder further including first clock circuit meansenabled for operation during one of the signal intervals of each of thereceived verification patterns, the comparing means including gatecircuit means responsive to the received verification signal, thetransponder signal, and the output of the first clock circuit means forproducing said output upon failure of verification.
 13. The combinationaccording to claim 12 wherein the first and second binary conditions arebinary ''''1'''' and binary ''''0, '''' respectively and the signalformat of the verification signal is such that the verification patternfor a binary ''''1'''' received from the transponder unit is in the formof a mark pulse of a first predetermined length followed by a spacepulse of a first predetermined length and wherein the verificationpattern for a binary ''''0'''' received from the transponder unit is inthe form of a mark pulse of a second predetermined length followed by aspace pulse of a second predetermined length, the length of at least oneof the mark or space pulses used for verifying a binary ''''1'''' beingdifferent from the length of the corresponding mark or space pulses inthe verification pattern for a binary ''''0,'''' with the gate circuitmeans including first and second verifier gates, the first gate beingenabled by a binary ''''1'''' from the transponder and the second gatebeing enabled by a binary ''''0'''' from the transponder, with pulsesfrom the first clock means being applied successively to the first andsecond verifier gates to produce outputs therefrom coinciding with theexpected mark-to-space transitions in the verification patterns, andmeans responsive to the verification signal and the outputs of the firstand second verifier gates for producing said output upon failure of themark-to-space transitions of the verification signal to occur during thetime an output is present from the first or second verifier gate. 14.The combination according to claim 12 further including a multi-stageshift register in the transponder with further gate circuit meansinterconnecting the output and input of the shift register to cause theregister to be operated as a maximum sequence counter; means responsiveto the interrogation signals for supplying shift pulses to the shiftregister; means responsive to a first predetermined code pattern storedin the shift register for enabling the transmission initiating means andfor disabling the further gate means, permitting operation of theregister as a shift register means responsive to operation of thetransmission initiating means for storing a predetermined code patternin the shift register corresponding to the sequence of first and secondbinary conditions to be transmitted from said transponder, the output ofthe final stage of the shift register providing the transponder output,and means responsive to pulse transitions in the received verificationsignal patterns for providing shift pulses for the shift register.
 15. Atransponder for use in a signalling system including an interrogationstation transmitting a sequence of interrogation signals, thetransponder including in combination: a multistage shift register means,having at least an input stage and an output stage, each stage of theshift register means capable of being set to either first or secondstates of operation corresponding to two binary conditions and thestages storing an initial sequence of binary conditions upon initialenergization; means responsive to the interrogation signals forproViding a sequence of shift pulses to the shift register to shift thesame; means coupled with the input stage of the shift register forcausing the shift register to be filled with a first predeterminedpattern of binary conditions in response to the application of shiftpulses thereto; means coupled with the shift register for sensing thestorage of said first predetermined pattern therein to produce a controlsignal; means responsive to the control signal for supplying a secondpredetermined binary sequence for storage in the shift register; andgate means responsive to the control signal and the output of the outputstage of the shift register for providing an output signal train fromthe transponder.
 16. The combination according to claim 15 wherein thefirst predetermined pattern is all stages of the shift register set tosaid first state of operation.
 17. The combination according to claim 15whereby the initial binary sequence established in the shift registerupon initial energization is a random sequence and the means for causingthe shift register to be filled with a first predetermined pattern ofbinary conditions includes second gate means responsive to the output ofthe output stage of the shift register for causing the register to beoperated as a maximum sequence counter, the second gate means beingdisabled in response to said control signal.
 18. The combinationaccording to claim 15 further including means for transmitting saidoutput signal train from the transponder and wherein the interrogationstation further transmits a sequence of signals uniquely verifyingsignals received by the interrogation station from the transponder, thetransponder further including means responsive to the receipt of theverification signals for providing shift pulses to the shift register.19. A buffer storage circuit for temporarily storing messages in theform of a binary bit train of a predetermined length supplied to thebuffer storage circuit at one bit rate and removed from the bufferstorage circuit at a second bit rate including in combination: aplurality of storage register means each having a capacity for storingat least one of said messages; input control means for sequentiallyenabling the storage registers for the receipt of an input message;input load means responsive to enabling of a register by the inputcontrol means to cause the storage of information therein at the bitrate of an input message; first means coupled with the storage registermeans and responsive to the storage to capacity of a storage registermeans for causing the input control means to enable the next register inthe sequence for the receipt of an input message; register unloadcontrol means; and second means coupled with the storage register meansand responsive to the storage to capacity of a register for enabling theregister unload control means to remove the message from the register atsaid second bit rate.
 20. The combination according to claim 19 furtherincluding inhibiting means responsive to the storage to capacity of allof said plurality of registers for inhibiting operation of the inputload means.
 21. The combination according to claim 20 wherein the secondmeans further senses completion of removal of a message from a registerby the unload control means to enable the unload control means to removea message from the next filled register in the sequence.
 22. Thecombination according to claim 21 wherein the input control meansincludes a first counter means having a predetermined number of outputscorresponding to the number of register means and the second meansincludes a second counter means having a predetermined number of outputscorresponding to the number of register means and advanced to enableremoval of messages sequentially from the register means, and whereinthe inhibiting means includes first gating means responsive tocorresponding outputs from the first and second counter means indicativEthat information has not been removed from the register to which thefirst counting means has progressed for inhibiting operation of theinput load means and further includes second gating means responsive toa combination of outputs of the first and second counter means, with theoutput of the second counter means corresponding to the register justprior to the one in the sequence which is enabled by an output from thefirst counter means, for inhibiting operation of the register unloadcontrol means.
 23. A dual mode register circuit including incombination: a multistage shift register means having at least an inputstage and an output stage, each stage of the shift register meanscapable of being set to either first or second states corresponding totwo binary conditions, and the stages storing information in the form ofan initial sequence of binary conditions upon initial energizationthereof; means for providing a sequence of shift pulses to the registermeans to shift said information from the input stage to the outputstage; first gate means responsive to the output of the output stage ofthe register means for supplying input signals to the input stage of theregister means to cause the register means to be operated as a maximumsequence counter; means responsive to the storage of a predeterminedinformation pattern in the register means for producing a controlsignal; means responsive to the control signal for supplying apredetermined binary sequence for storage in the register means; meansresponsive to the control signal for disabling operation of the gatemeans to cause a predetermined binary condition to be applied to theinput stage of the register means; and second gate means responsive tothe control signal and the output of the output stage of the registermeans for providing an output signal train from the register means. 24.The combination according to claim 23 wherein the first gate meanscoupled with the output stage of the register means has at least firstand second inputs, with the first input thereof being connected theoutput of the output stage of the register means; and wherein the meansfor producing the control signal is a bistable multivibrator havingfirst and second states of operation, and being set to a first state ofoperation supplying an enabling signal to the second input of the firstgate means, with the output of the first gate means being coupled withthe input of the input stage of the shift register and operating inresponse to the output of the output stage of the shift register tocause the shift register to be operated as a maximum sequence counter,the combination further including means coupled with the register meansand responsive to the storage of the predetermined information patternfor causing the bistable multivibrator to change states of operation,thereby disabling the first gate means, causing a predetermined input tobe supplied to the input stage of the register means so that furtherapplication of shift pulses thereto causes the register means to operateas a shift register.
 25. A signalling system for identifying andmonitoring a transponder unit with an interrogation station transmittinginterrogation and verification signals, the system including incombination: a multi-stage register means in the transponder and havingat least an input stage and an output stage, each stage of the shiftregister means capable of being set to either first or second stages ofoperation corresponding to two binary conditions and the stages storingan initial random sequence of binary conditions upon initialenergization thereof; means responsive to the interrogation signals forproviding a sequence of shift pulses to the shift register to shiftinformation stored therein from the input stage to the output stage;first gate means responsive to the output of the output stage of theshift register means for supplying signals to the input stage thereof tocause the regisTer means to operate as a maximum sequence counter; meansresponsive to the storage of a maximum sequence count in the shiftregister for producing a control signal; means responsive to the controlsignal for disabling the gate means, to enable the register means to beoperated as a shift register; transponder signal input means responsiveto the control signal for supplying a predetermined unique binarysequence for storage in the shift register means; transmission means inthe transponder unit responsive to the control signal and the output ofthe output stage of the register means for providing an output signaltrain from the transponder; means in the interrogation stationresponsive to the signals received by the interrogation station from thetransponder unit for generating a sequence of verification signalsverifying said received signals; means responsive to the verificationsignals for providing a sequence of shift pulses to the shift registerto shift the same; means in the transponder unit for comparing thereceived verification signals with the transmitted unique binarysequence for producing an output upon failure of verification; and meansfor terminating transmission from the transponder unit and for enablingthe first gate means to cause the register means once again to beoperated as a maximum sequence counter, the initial count stored thereincorresponding to the states of the shift register stages at the timetransmission is terminated, said means for terminating transmissionfurther causing the control signal to be terminated and the transponderunit to be rendered responsive to transmitted interrogation signals forproviding said sequence of shift pulses to the shift register.